Nanowire Transistor Etch Stop Layers for Source-Drain Protection
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Solution Overview
Problem
In gate last fabrication schemes for nanowire transistors, the source and drain electrodes are unintentionally damaged during the formation of the gate electrode, leading to poor transistor characteristics and reduced device yield, and current solutions to protect these electrodes result in larger devices with reduced drive current and transistor density.
Innovation Solution
Incorporating an etch stop layer between the source and drain electrodes and the nanowire channel region, made of materials similar to the nanowire with added dopants for improved etch resistance, to prevent unintentional removal of the electrodes without increasing channel length or spacer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrode formation is performed in gate last fabrication scheme, then nanowire transistor can be fabricated with good gate control, but source electrode and drain electrode are unintentionally removed leading to poor transistor characteristics
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the source/drain electrodes and the nanowire channel region. This layer selectively resists the etching process used to form the gate electrode, preventing the etchant from attacking and removing the source/drain electrodes while still allowing the gate electrode formation to proceed.
Solution Approach 2:
The etch stop layer is formed in advance before the gate electrode formation process. By pre-positioning this protective layer with appropriate etch resistance, the source/drain electrodes are protected during subsequent processing steps before any damage can occur.
2Reliability
If current protection solutions are implemented to protect source and drain electrodes, then electrode damage is reduced, but device size increases and transistor density decreases
Solution Approach 1:
The etch stop layer is applied locally only in specific regions where protection is needed - between the source/drain electrodes and the nanowire channel region - rather than uniformly across the entire device. This localized approach provides targeted protection while minimizing the impact on overall device dimensions and maintaining high transistor density.
Solution Approach 2:
The etch stop layer is designed with specific material composition and thickness parameters that provide sufficient etch resistance to protect the electrodes while keeping the layer thin enough to maintain compact device dimensions. By optimizing these parameters, protection is achieved without sacrificing transistor density.
3Reliability
If etch stop layer is introduced to protect electrodes, then electrode integrity is maintained, but device complexity increases
Solution Approach 1:
The etch stop layer formation is merged with existing fabrication process steps, such as combining it with the nanowire formation process or other intermediate steps. By integrating this protective layer formation into the existing process flow rather than adding a completely separate step, the increase in device complexity is minimized while still achieving electrode protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The etch stop layer effectively protects the source and drain electrodes, maintaining transistor integrity and density while preserving drive current and gate control, thus enhancing device yield and performance.
Implementation Method 1
an etch stop layer between a source electrode or a drain electrode and a channel region including a nanowire... with some added dopants to improve its etch resistance
Data Source
AI summary
Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.