Semiconductor-Superconductor Nanowire Fabrication for Scalable Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating semiconductor-superconductor nanowires face challenges with scalability, limiting the size and complexity of nanowire networks due to issues like 'soft gap' states caused by disorder at the semiconductor-superconductor interface, which lead to decoherence in Majorana zero modes.
Innovation Solution
A method combining selective area growth (SAG) of semiconductor materials with epitaxial superconductor deposition, using a dielectric mask to define growth regions and angle the particle beam for direct contact and controlled superconductor coverage, enabling the fabrication of high-quality, scalable semiconductor-superconductor platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to create semiconductor-superconductor nanowires, then the interface quality can be improved, but the scalability is limited
Solution Approach 1:
The fabrication process is segmented into distinct phases: masking phase where a dielectric mask defines regions, selective area growth phase where semiconductor nanowires grow only in exposed regions, and superconductor growth phase where superconducting material is deposited. This segmentation enables precise interface control while scaling to large networks through parallel growth in multiple exposed regions.
Solution Approach 2:
The dielectric mask creates locally different growth conditions across the substrate. Semiconductor material is selectively grown only in exposed regions, creating high-quality SE/SU interfaces at specific locations while maintaining scalability across the entire substrate area through controlled local growth.
2Ease of manufacture
If the semiconductor-superconductor interface has disorder, then fabrication is easier, but soft gap states cause decoherence
Solution Approach 1:
The dielectric mask is formed beforehand to predefine the exact regions where semiconductor nanowires will grow. This preliminary structuring ensures that subsequent superconductor deposition occurs only at the intended SE/SU interfaces, eliminating disorder from misaligned interfaces while maintaining fabrication simplicity through a straightforward sequential process.
Solution Approach 2:
The dielectric mask acts as an intermediary element that mediates between the semiconductor growth and superconductor deposition processes. It precisely defines the interface locations, ensuring clean SE/SU boundaries without disorder, while the mask itself can be removed or integrated into the final structure.
3Productivity
If larger nanowire networks are fabricated, then quantum computing capability increases, but interface disorder increases causing more decoherence
Solution Approach 1:
The large substrate is divided into multiple exposed regions defined by the dielectric mask pattern. Each exposed region independently produces high-quality SE/SU interfaces through selective area growth, while the overall network scales to large sizes by having many such regions in parallel. This segmentation maintains interface quality regardless of network size.
Solution Approach 2:
The fabrication method changes the growth parameters through the dielectric mask configuration, controlling where and how semiconductor and superconductor materials grow. By adjusting mask patterns and growth conditions, large networks can be fabricated while maintaining precise interface quality through controlled local growth parameters in each exposed region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach produces stable Majorana modes with reduced decoherence, allowing for the creation of large and complex nanowire networks suitable for topological quantum computations, with reproducible and scalable fabrication of high-quality SE/SU interfaces.
Implementation Method 1
In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. The semiconductor material in the one or more exposed regions forms a network of in-plane nanowires.
Implementation Method 2
The layer of superconducting material may be epitaxially grown in the superconductor growth phase. The layer of superconducting material may be epitaxially grown using molecular beam epitaxy (MBE).
Implementation Method 3
The layer of superconducting material may be formed, in the superconductor growth phase, using a beam. The beam may have a non-zero angle of incidence relative to the normal of a plane of the substrate.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor- superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.