Nanowire FET Back Gate Support for Threshold Control
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Solution Overview
Problem
Current semiconductor technologies face challenges such as short channel effects, high manufacturing costs, and reliability issues due to the continuous scaling down of semiconductor devices, particularly with Ultra Thin Buried oxide and Fin Field Effect Transistor (FinFET) devices, which struggle to control threshold voltage and maintain structural integrity.
Innovation Solution
The introduction of a semiconductor arrangement featuring a substrate with a back gate and pairs of nanowires on opposite sides, separated by back gate dielectric layers, forming a sandwich nanowire configuration that allows for effective threshold voltage control and improved reliability through the back gate's support mechanism, while utilizing existing FinFET manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ultra Thin Buried oxide (UTBB) substrate is used to suppress short channel effects, then short channel effects are suppressed, but manufacturing cost increases significantly and self-heating problems occur
Solution Approach 1:
The patent replaces the expensive UTBB substrate with a standard silicon substrate, using a sacrificial layer that is intentionally designed to be removed after serving its temporary purpose of defining the nanowire structure. This approach uses cheaper, temporary structures to achieve the desired device performance without the high cost of specialized substrates.
2Power
If fin height is increased in FinFET device to improve drive current per unit footprint, then drive current is improved, but threshold voltage control becomes ineffective
Solution Approach 1:
The patent transitions from a planar FinFET structure to a three-dimensional nanowire configuration where the channel is surrounded by the gate on multiple sides. This dimensional change allows effective threshold voltage control through the back gate while maintaining high drive current through the increased surface area of the nanowire channel.
3Power
If fin is formed as nanowire to create nanowire FET, then drive current is improved, but threshold voltage control becomes ineffective and nanowire tends to collapse during manufacture
Solution Approach 1:
The patent introduces a back gate as an intermediary structure that serves dual purposes: providing mechanical support to prevent nanowire collapse during manufacturing and enabling effective threshold voltage control. The back gate acts as a mediator between the nanowire channel and the control circuitry, solving both the structural stability and electrical control problems.
4Productivity
If continuous scaling down is performed to improve device density, then device density is improved, but short channel effects worsen and manufacturing becomes more difficult
Solution Approach 1:
The patent employs a vertical nanowire channel structure with back gate control, transitioning from planar scaling to three-dimensional device architecture. This dimensional change allows continued scaling and improved device density while maintaining effective electrostatic control over the channel, preventing short channel effects even as dimensions are reduced.
Data Source
AI summary
Semiconductor arrangements and methods for manufacturing the same. The arrangement may include: a substrate; a back gate formed on the substrate; at least one pair of nanowires disposed on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective nanowires.