Nanowire FET Diameter Control via Local Quality and Preliminary Action
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Solution Overview
Problem
Current methods for fabricating nanowire field effect transistors (FETs) face challenges in forming nanowires with varying diameters on a single substrate, which affects the threshold voltage and drive currents, limiting the flexibility of these devices.
Innovation Solution
A method involving height adjustments and annealing processes on a silicon-on-insulator substrate to form nanowire structures with different diameters by modifying the thickness of material layers in defined regions, allowing for the creation of multiple nanowire structures with distinct diameters on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a blanket and conformal deposition of gate dielectric and gate conductor is performed, then the gate conductor covers all surfaces of suspended nanowires, but the gate material fills the undercut at the edge of source and drain regions, requiring additional etching steps to remove excess material
Solution Approach 1:
The patent applies preliminary action by forming a suspended nanowire structure before depositing the gate material. The nanowire is suspended over a cavity, allowing the gate dielectric and gate conductor to be deposited conformally around all surfaces of the nanowire in a single blanket deposition process, eliminating the need for subsequent etching steps to remove excess gate material from undercut regions.
Solution Approach 2:
The patent utilizes another dimension by creating a three-dimensional suspended nanowire structure that extends over a cavity. This vertical suspension allows the gate material to wrap around the nanowire from all directions (top, bottom, and sides) simultaneously during conformal deposition, achieving gate-all-around coverage without requiring complex multi-step patterning and etching processes.
2Reliability
If nanowires are suspended to enable gate-all-around coverage, then the gate conductor can cover all surfaces of the nanowires, but the isotropic etching process creates overhang/undercut at the edge of source and drain regions
Solution Approach 1:
The patent performs the suspension step before gate deposition, allowing the nanowire to be suspended over a cavity. This preliminary suspension creates a geometry where the subsequent conformal gate deposition naturally achieves complete coverage without creating problematic overhangs or undercuts at the source and drain edges, as the gate material deposits uniformly around the suspended structure.
Solution Approach 2:
By transitioning to a three-dimensional suspended configuration, the patent enables the gate material to access and cover all surfaces of the nanowire including the bottom surface, which would be inaccessible in a planar configuration. This dimensional change eliminates the need for undercut formation and achieves precise edge definition at the source and drain regions.
3Ease of manufacture
If current fabrication methods are used, then nanowire FETs can be manufactured, but all nanowires on a substrate have the same diameter, limiting flexibility in threshold voltage and drive current control
Solution Approach 1:
The patent applies local quality by introducing a thickness adjustment layer that is selectively positioned under specific nanowire regions. This layer has a different thickness than the surrounding areas, causing the underlying nanowires to have different diameters after release. This enables different threshold voltages and drive currents for nanowires in different regions while maintaining batch processing capability.
Solution Approach 2:
The patent utilizes parameter changes by modifying the thickness of the material layer in specific regions through the thickness adjustment layer. This thickness variation directly controls the diameter of the released nanowires, allowing tuning of electrical parameters such as threshold voltage and drive current for different nanowire FETs on the same substrate, all within a single batch fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of nanowire FETs with varying threshold voltages and drive currents, enhancing the flexibility and performance of the transistors by allowing for tailored nanowire diameter configurations.
Implementation Method 1
an anneal process is performed, to transform each first channel structure into a first nanowire structure, and to transform each second channel structure into a second nanowire structure
Data Source
AI summary
The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.