Nanowire FET With Inner Outer Gates For Channel Control
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Solution Overview
Problem
In nanowire field-effect transistors (NFETs), particularly in the Si/SiGe material system, it is challenging to form an inner gate dielectric due to the zero conduction band offset between Si and SiGe, which limits control over the nanowire channel and exacerbates short-channel effects.
Innovation Solution
A semiconductor device with a suspended semiconductor nanowire inner gate and a first epitaxial dielectric layer surrounding the inner gate, where a second dielectric layer is covered by a gate conductor patterned into a gate line, allowing for improved control over the channel region by moving the charge centroid and maximum leakage point closer to the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an inner gate dielectric is formed in Si/SiGe material system, then gate control over nanowire channel is improved, but manufacturing difficulty increases due to zero conduction band offset
Solution Approach 1:
The patent introduces an intermediary material layer between the SiGe nanowire channel and the gate electrode. This intermediate layer serves as a bridge that enables effective gate control while circumventing the manufacturing challenges posed by the zero conduction band offset in direct Si/SiGe interfaces. The intermediary layer allows for proper dielectric formation and charge control without requiring direct contact between incompatible materials.
2Reliability
If inner gate structure is implemented, then control over nanowire channel is enhanced, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functional components: an inner gate dielectric layer positioned within the nanowire structure, an intermediate material layer for interface management, and an outer gate electrode. This segmentation allows each layer to perform its specific function optimally while simplifying the overall fabrication process compared to attempting to form a monolithic inner gate structure.
Solution Approach 2:
The patent implements a nested gate structure where the inner gate dielectric and intermediate layer are positioned within the nanowire channel region, surrounded by the gate electrode. This nested configuration enables enhanced gate control by placing control elements closer to the channel while maintaining a manageable external structure for fabrication and integration.
3Ease of manufacture
If conventional gate structure is used, then manufacturing is easier, but short-channel effects are exacerbated
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional inner gate configuration where the gate dielectric and control elements are positioned within the nanowire channel volume. This dimensional change enables superior electrostatic control over the channel, suppressing short-channel effects by reducing the distance between the gate and the channel region, while the segmented fabrication approach maintains manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances gate control over the nanowire channel, reducing short-channel effects and improving device performance by using epitaxial growth techniques to deposit dielectric layers and a gate conductor, specifically suitable for III-V semiconductor materials like InGaAs.
Implementation Method 1
a first epitaxial dielectric layer which surrounds a nanowire inner gate
Implementation Method 2
The first epitaxial dielectric layer surrounds an epitaxial semiconductor channel
Data Source
AI summary
A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line.