III-V Nanowire FETs with Conformal Gate and Nitrogen Doping
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Solution Overview
Problem
Achieving reliable gate control in non-planar III-V nanowire field effect transistors is challenging due to poor quality native oxides and sub-stoichiometric surfaces, particularly with high-k gate dielectrics, which lead to increased trapped charge and interface trap density.
Innovation Solution
Implementing a nitrogen-doped high-k gate dielectric with a conformal gate electrode and non-directional nitrogen doping to reduce trapped charge and improve gate control, utilizing atomic layer deposition and thermal annealing to ensure uniform nitrogen distribution proximal to the III-V semiconductor interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate dielectric is used in non-planar III-V nanowire FET, then gate control reliability is improved, but interface trap density increases due to poor quality native oxides and sub-stoichiometric surfaces
Solution Approach 1:
The patent applies nitrogen doping to modify the chemical composition and electronic properties of the gate dielectric interface. By introducing nitrogen atoms into the high-k dielectric layer adjacent to the III-V semiconductor interface, the interface trap density is reduced while maintaining the high-k characteristics, thus resolving the contradiction between reliability improvement and trap density reduction
Solution Approach 2:
A nitrogen-containing interface layer is introduced as an intermediary between the high-k gate dielectric and the III-V nanowire semiconductor. This intermediate layer passivates the sub-stoichiometric surface and reduces interface traps, enabling reliable gate control without the harmful effects of direct contact between the high-k dielectric and poor-quality native oxide
2Reliability
If conformal gate electrode is implemented to wrap around nanowire, then gate control is enhanced, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is designed with a conformal curved structure that wraps around the cylindrical nanowire channel. This curved geometry provides all-around gate control for enhanced field effect, while the continuous wraparound structure simplifies the overall device architecture compared to planar alternatives with equivalent control
3Reliability
If nitrogen doping is applied to reduce trapped charge, then gate control improves, but process complexity increases due to additional nitridation and annealing steps
Solution Approach 1:
The patent combines multiple functions into integrated process steps: the nitrogen doping is performed during or alongside the high-k dielectric deposition process, and the thermal annealing step simultaneously activates the nitrogen doping, repairs interface defects, and stabilizes the dielectric structure. This merging of steps reduces overall process complexity while achieving the desired gate control improvement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in low interface trap density and improved gate control in highly scaled non-planar FETs, enhancing the performance of III-V nanowire transistors by reducing oxidation and maintaining a uniform semiconductor surface treatment.
Implementation Method 1
non-directional nitrogen doping to reduce trapped charge and improve gate control, utilizing atomic layer deposition and thermal annealing to ensure uniform nitrogen distribution proximal to the III-V semiconductor interface
Implementation Method 2
utilizing atomic layer deposition and thermal annealing to ensure uniform nitrogen distribution proximal to the III-V semiconductor interface
Implementation Method 3
utilizing atomic layer deposition and thermal annealing to ensure uniform nitrogen distribution
Data Source
Figure 1A~1B
Figure 1C
Figure 1D
AI summary
A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.