Nanowire FET Standard Cell Layout for Regular Pad Pitch
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Solution Overview
Problem
Current semiconductor integrated circuit devices with nanowire FETs lack effective layout configurations, leading to increased off-current and power consumption due to excessive scaling, and there is a need for a manufacturing method that reduces process-induced variation and improves yield.
Innovation Solution
A semiconductor integrated circuit device layout featuring standard cells with nanowire FETs, where pads are arranged at a regular pitch along the direction of the nanowire, allowing for easy manufacturing and reducing process-induced variation by ensuring regular pad arrangement and efficient connection of transistors in series or parallel configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor gate length is scaled down to increase integration, then more transistors can be integrated and operating rate improves, but off-current increases and power consumption increases
Solution Approach 1:
The patent transitions from conventional two-dimensional planar transistors to three-dimensional nanowire FETs with gate-all-around structure. The nanowire channel extends in the vertical dimension, allowing the gate to surround the channel from all directions (top, bottom, and sides), creating a true 3D control structure that improves carrier confinement and reduces off-state leakage current while maintaining small footprint for high integration density.
2Ease of manufacture
If standard cell layout is not specifically optimized for nanowire FETs, then manufacturing process variation increases and yield decreases
Solution Approach 1:
The standard cell layout is segmented into modular units with standardized pad arrangements. Each nanowire FET occupies a defined spatial grid, and pads are positioned at regular intervals along the nanowire direction. This segmentation allows the layout to be divided into repeatable modules that can be manufactured with consistent precision, reducing process variation and improving yield.
Solution Approach 2:
The patent establishes specific geometric parameters for the standard cell layout, including pad pitch, nanowire length, and gate positioning. By defining these parameters as fixed values rather than variable dimensions, the manufacturing process can be optimized for these specific dimensions, reducing variability and improving manufacturing precision and yield.
Data Source
AI summary
In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.