Gate-All-Around Nanowire FET Fabrication via Replacement Gate Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fabricating gate all around nanowire FETs is challenging due to nanowire damage during the fabrication process and critical dimension loss in conventional gate-first processes, which affects scalability and layout efficiency.
Innovation Solution
A method involving the formation of semiconductor fins with a sequential stack of buffered, sacrificial, and channel layers, followed by the creation of dummy gate structures, gap filler deposition, and removal to form trenches, allowing for the release of nanowire channels and the formation of replacement gates that surround the nanowires in a gate all around configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate-first process is used, then gate material can be deposited early, but critical dimension loss of gate line occurs and nanowire damage happens
Solution Approach 1:
The nanowire is formed and protected within the fin structure before gate deposition. The gate is deposited after the fin structure is complete, allowing the nanowire to be prepared and protected in advance while maintaining precise dimensional control throughout the process.
Solution Approach 2:
The fin structure serves as an intermediary that protects the nanowire during fabrication. The nanowire is embedded within the fin, and the fin acts as a protective scaffold that prevents damage while allowing precise gate formation.
2Reliability
If nanowire is suspended using landing pad region, then nanowire can be supported, but layout efficiency is reduced
Solution Approach 1:
Instead of using lateral landing pads, the support structure extends into the vertical dimension. The gate wraps around the nanowire in three dimensions, providing support through the gate-all-around configuration rather than through lateral pad structures.
Solution Approach 2:
The gate structure serves multiple functions simultaneously: it provides the electrical gating function, supports the nanowire mechanically, and eliminates the need for separate landing pad structures, thereby improving layout efficiency while maintaining nanowire reliability.
3Adaptability or versatility
If gate material is removed beneath source/drain region, then gate-all-around structure can be formed, but critical dimension loss and process complexity increase
Solution Approach 1:
The gate material is selectively removed only from the regions beneath the source and drain extensions, while being retained in the channel region. This extraction approach creates the gate-all-around structure without requiring complete gate removal, thereby simplifying the process while achieving the desired configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach protects the nanowire integrity throughout the process, enhances crystal quality, reduces crystal defect density, and lowers OFF-state leakage current, enabling the integration of high-quality III-V nanowire FETs with improved scalability and reduced drive voltages.
Implementation Method 1
releasing a portion of the channel layer of the semiconductor fins located within the trenches by removing portions of the sacrificial layer located beneath the portion of the channel layer within the trenches
Implementation Method 2
performing an epitaxial growth process on the patterned channel layer portions of the semiconductor fins to transform the patterned channel layer portions into a continuous channel layer and to form a source region and a drain region
Data Source
AI summary
A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.