Gate-All-Around Nanowire FET Fabrication via Selective Oxidation
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Solution Overview
Problem
The fabrication of nanowire field-effect transistors, particularly gate-all-around MOSFETs, is challenging due to the small cross-sectional area of single nanowires, limiting drive current, and existing methods struggle with complex geometry and scalability in CMOS processing.
Innovation Solution
A method involving the formation of stack structures with alternating semiconductor layers, selective oxidation, and removal of oxidized material to expose vertically-aligned nanowires, facilitating the creation of gate-all-around structures with enhanced control over the channel and reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around configuration is implemented to increase inversion layer extent, then gate controllability is improved, but device fabrication complexity increases
Solution Approach 1:
The channel is segmented into multiple parallel nanowires, each surrounded by its own gate. This segmentation allows the gate to control the inversion layer from all directions (gate-all-around), significantly improving gate controllability while the modular nanowire structure enables systematic fabrication approaches
Solution Approach 2:
The gate structure is nested around the nanowire channel in a gate-all-around configuration, with the gate completely surrounding the channel from top, bottom, and sidewalls. This nested geometry maximizes gate control over the inversion layer while the patent provides systematic methods for achieving this complex nested structure through selective oxidation and sacrificial layer techniques
2Reliability
If single nanowire is used to reduce short-channel effects, then gate controllability is improved, but drive current is limited due to small cross-sectional area
Solution Approach 1:
Multiple nanowires are merged into a single device structure, with each nanowire maintaining its individual gate-all-around control. The combined drive current of multiple nanowires in parallel exceeds that of a single nanowire, solving the power limitation while each nanowire individually maintains excellent short-channel effect control through its nanoscale dimensions
Solution Approach 2:
The invention transitions from a single nanowire to multiple nanowires arranged in parallel, effectively adding a dimensional aspect to the device architecture. This multi-nanowire arrangement increases the total cross-sectional area for current flow while maintaining the nanoscale dimensions of individual nanowires that provide excellent electrostatic control and short-channel effect suppression
3Productivity
If transistor size is reduced to scale down CMOS devices, then integration density is improved, but fabrication precision requirements increase
Solution Approach 1:
The selective oxidation process utilizes the self-service principle where the oxidized material naturally forms a conformal layer around the nanowire structure, and the subsequent removal of oxidized material self-alignedly exposes the nanowire for gate formation. This self-aligned approach reduces the need for additional lithography steps and alignment precision, enabling scalable fabrication of high-density nanowire devices
Solution Approach 2:
The invention employs parameter changes in the oxidation process, using controlled oxidation conditions to selectively oxidize specific regions of the stack structure. By adjusting oxidation parameters (temperature, time, atmosphere), the process achieves precise control over oxidized material formation and removal, enabling high-precision nanowire fabrication that scales to high integration densities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases drive current per device area by forming multiple nanowires in parallel alignment, enabling improved gate controllability and minimizing short-channel effects, while being compatible with CMOS processing.
Implementation Method 1
selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending therein surrounded by oxidized material of the at least one stack structure
Data Source
AI summary
Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.