Stacked Nanowire FET Spacers for Higher Current Density
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors face challenges in achieving high device current density and on-off current ratios due to limitations in controlling semiconductor channels effectively.
Innovation Solution
A method for forming nanowire field effect transistors involves vertically stacking semiconductor nanowires with sacrificial layers, using epitaxial deposition to align crystallographic orientations, and forming dielectric spacers and source/drain regions to enhance channel control, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor structures are used, then manufacturing is simpler, but device current density per device area is lower
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional nanowire configurations. Multiple nanowires are stacked vertically to form the channel, enabling gate-all-around control from all directions (top, bottom, and sidewalls). This vertical stacking increases the effective channel area within the same footprint, thereby increasing device current density per device area while maintaining compact form factor.
Solution Approach 2:
The gate structure is nested around each nanowire channel in a gate-all-around configuration, with the gate wrapping completely around the channel from all directions. This nested arrangement provides maximum electrostatic control over the channel, enabling superior on-off current ratios. The dielectric spacers are also nested between adjacent nanowires to provide electrical isolation while maintaining compact vertical spacing.
2Reliability
If conventional channel control methods are used, then device structure is simpler, but on-off current ratios are lower
Solution Approach 1:
The gate control is extended from planar (top-only) control to three-dimensional gate-all-around control that wraps around the nanowire channel from all directions including top, bottom, and sidewalls. This multi-directional electrostatic control provides superior modulation of the channel, achieving higher on-off current ratios by effectively controlling carrier flow from all sides of the channel.
Solution Approach 2:
Dielectric spacer structures are introduced as intermediary elements positioned between adjacent nanowire channels. These spacers provide electrical isolation and prevent unwanted coupling between neighboring channels while allowing the gate to maintain control. The spacers act as mediators that enable independent control of each nanowire channel in the stack, improving overall device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances device current density and on-off current ratios by providing precise control over semiconductor channels, leading to improved transistor performance.
Implementation Method 1
epitaxial deposition to align crystallographic orientations
Data Source
AI summary
A semiconductor structure may be formed by: forming semiconductor nanowires over a substrate, wherein the semiconductor nanowires and the substrate are vertically spaced from one another by gaps, and wherein the semiconductor nanowires are suspended over the substrate by a support structure; performing at least two iterations of a sequence of processing steps that includes a flowable chemical vapor deposition process that deposits a respective dielectric material and an ultraviolet cure process that irradiates ultraviolet radiation to the respective dielectric material; and forming dielectric spacer structures having a lesser lateral extent than the semiconductor nanowires by isotropically etching the dielectric materials deposited by instances of the flowable chemical vapor deposition process and densified by instances of the ultraviolet cure process.