Nanowire FETs with Variable Thickness for Drive Current Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nanowire field effect transistors (FETs) face challenges in providing devices with varying drive current strengths and threshold voltages, as existing solutions involve costly and complex process integration with modulation of gate work-function, leading to variation concerns.
Innovation Solution
The method involves creating regions on a wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via nanowire channels, and reshaping these channels into nanowires with distinct thicknesses to achieve varying drive currents and threshold voltages, using techniques like oxidation, etching, and selective silicon epitaxy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate work-function modulation is used to achieve different drive current strengths and threshold voltages, then device performance variation is controlled, but process integration complexity and cost increase
Solution Approach 1:
The patent applies local quality by creating regions with different initial semiconductor thicknesses across the wafer. By masking specific regions and selectively thinning others, the invention achieves spatially varying nanowire thicknesses that directly control device characteristics without requiring complex gate work-function modulation processes throughout the entire fabrication sequence.
Solution Approach 2:
The invention performs preliminary action by establishing regions with different initial semiconductor thicknesses before nanowire formation. This pre-differentiation of thickness regions allows subsequent processing to naturally produce nanowires with different drive currents and threshold voltages, eliminating the need for complex post-formation gate modifications.
2Reliability
If gate work-function modulation is used to achieve different threshold voltages, then device characteristics are tailored, but manufacturing cost increases
Solution Approach 1:
The patent employs parameter changes by varying the initial semiconductor thickness parameter across different wafer regions through selective masking and thinning. This fundamental parameter variation propagates through the fabrication process to produce nanowires with inherently different threshold voltages and drive currents, providing a cost-effective alternative to gate work-function modulation.
3Reliability
If gate work-function modulation is used to achieve different drive current strengths, then device performance is optimized, but process variation concerns increase
Solution Approach 1:
By implementing local quality through spatially differentiated initial thickness regions, the patent creates deterministic variations in nanowire properties. This approach reduces process variation compared to global gate work-function modulation because each region's final nanowire characteristics are directly determined by its initial thickness rather than being subject to variations in subsequent gate modification processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the controlled fabrication of nanowires with different thicknesses, enabling the production of FETs with tailored drive currents and threshold voltages, thereby addressing the challenges of process integration and variation concerns in existing solutions.
Implementation Method 1
using techniques like oxidation, etching, and selective silicon epitaxy
Implementation Method 2
using techniques like oxidation, etching, and selective silicon epitaxy
Implementation Method 3
using techniques like oxidation, etching, and selective silicon epitaxy
Data Source
AI summary
A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.