Nanowire and Fin FET Coexistence via Segmented Gate Insulation
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Solution Overview
Problem
Current semiconductor technologies face challenges in coexisting FETs with low and high drive voltages on the same chip, particularly for nanowire FETs, which struggle to meet reliability requirements with thick gate insulating films.
Innovation Solution
A semiconductor device comprising a first field effect transistor with nanowire or nanosheet structure and a second field effect transistor with a Fin structure, where the channel structure units are spaced apart, allowing for the formation of gate insulating films and gate electrodes to achieve a balance between low and high drive voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a nanowire FET structure is used to achieve shorter gate length and lower drive voltage, then the gate length can be reduced below the limit of Fin FET, but it becomes difficult to satisfy reliability requirements with thick gate insulating films
Solution Approach 1:
The invention divides the semiconductor device into two separate regions: a first region containing nanowire FETs for low drive voltage applications, and a second region containing Fin FETs for high drive voltage applications. This segmentation allows each transistor type to be optimized for its specific voltage requirements without compromising the other, enabling both short gate lengths and thick gate insulating films to coexist in different parts of the device.
Solution Approach 2:
The invention applies different structural configurations to different regions of the semiconductor device. The first region uses nanowire structures with specific diameter ratios optimized for low voltage operation, while the second region uses Fin structures optimized for high voltage operation. This local differentiation allows each region to have the appropriate gate insulating film thickness and structural characteristics for its intended function.
2Reliability
If a thick gate insulating film is used to ensure reliability for high drive voltage FETs, then reliability is improved, but it becomes difficult to achieve the required performance for low drive voltage nanowire FETs
Solution Approach 1:
The semiconductor device is segmented into two functional regions: a first region with nanowire FETs operating at low drive voltages (0.5V to 1.0V) and a second region with Fin FETs operating at high drive voltages (1.5V to 3.0V). Each region has independently optimized gate insulating film thickness to match its operational requirements, allowing both low voltage performance and high voltage reliability to be achieved simultaneously in different parts of the device.
3Ease of manufacture
If the same gate insulating film thickness is used for both nanowire FETs and Fin FETs, then manufacturing is simplified, but it is impossible to satisfy both low drive voltage and high drive voltage requirements
Solution Approach 1:
The invention divides the device into two regions with different gate insulating film thicknesses: the first region has a thinner gate insulating film (5nm to 15nm) optimized for nanowire FETs, while the second region has a thicker gate insulating film (15nm to 30nm) optimized for Fin FETs. This segmentation enables each region to have independently optimized electrical characteristics for its specific voltage requirements.
Solution Approach 2:
Different gate insulating film thicknesses are applied to different regions based on their specific functional requirements. The first region uses thinner films for low voltage operation, while the second region uses thicker films for high voltage operation. This local differentiation allows the device to achieve both low drive voltage performance and high drive voltage reliability simultaneously.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure, and a second field effect transistor having a Fin structure, in which the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor.