Nanowire Structure Manufacturing via Fin Segmentation and Recessing
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Solution Overview
Problem
Conventional planar MOS transistors face challenges in scaling down below 65 nm, necessitating the development of non-planar transistor technologies like FinFETs and nanowire FETs for enhanced performance and miniaturization, but existing methods struggle to efficiently convert fin structures into nanowires for improved integrated circuit performance.
Innovation Solution
A manufacturing method involving the formation of patterned insulation layers and shallow trench isolation to convert a part of a fin into a nanowire, including recessing processes to expose and separate upper and lower fin sections, allowing for the formation of nanowires with varying widths and alignment in a vertical projective direction, and the use of epitaxial layers to enhance transistor mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar MOS transistor scaling is continued below 65 nm, then manufacturing simplicity is maintained, but device performance and miniaturization goals cannot be achieved
Solution Approach 1:
The fin structure is segmented into multiple sections through selective recessing: the upper fin portion is converted to a nanowire while the lower fin portion is retained, creating a hybrid structure that combines advantages of both finFET and nanowire FET architectures
Solution Approach 2:
The invention transitions from a two-dimensional planar MOS structure to a three-dimensional nanowire structure by converting the upper fin portion into a suspended nanowire, enabling gate-all-around control and improving device performance at scaled dimensions
2Length of moving object
If FinFET technology is adopted for miniaturization, then smaller size and higher performance are achieved, but the conversion to nanowire structure becomes complex
Solution Approach 1:
The fin is divided into distinct upper and lower portions through selective recessing processes, allowing the upper portion to be converted to nanowire while maintaining the lower fin structure, thus achieving nanowire benefits without complete structural redesign
Solution Approach 2:
Patterned insulation layers are formed on the fin surface before the recessing process, providing a mask that defines the nanowire formation regions and simplifies the subsequent etching and conversion steps
3Manufacturing precision
If multiple nanowires are formed through repeated processes, then alignment and integrity are improved, but manufacturing time and complexity increase
Solution Approach 1:
Multiple patterned insulation layers are formed in advance on different portions of the fin, creating pre-defined masks that enable simultaneous or sequential formation of multiple nanowires with precise alignment, reducing the need for repeated alignment operations
Solution Approach 2:
The formation of multiple nanowires is merged into a single integrated process flow where patterned insulation layers are formed once, followed by a unified recessing process that creates multiple nanowires simultaneously, rather than forming each nanowire separately
Data Source
AI summary
A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire.