Nanowire Stack GAA Epitaxy With Flat Trench Base Control

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Solution Overview

Problem

The challenge in forming gate-all-around (GAA) devices is to achieve precise control over the growth of epitaxy layers within trenches, particularly due to the lattice mismatch and crystalline facet orientations, which affects the formation of flat surfaces and channel regions in CMOS transistors, leading to short-channel effects and compromised electrostatic control.

Innovation Solution

The technique involves modifying the trench bottom and sidewall facets through crystallographic anisotropic etching to create a recess with specific angles, allowing for the growth of silicon germanium epitaxy layers that preferentially fill the trench bottom while avoiding the sidewalls, resulting in a flat base layer for subsequent epitaxy deposition, enabling the formation of GAA devices with improved channel control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If epitaxy layers are grown directly in trenches with standard bottom surfaces, then the growth process is simple, but the resulting surfaces are non-flat and channel control is compromised

Engineering Contradiction:
Improveflatness of epitaxy layer surfaceVSAvoidcomplexity of trench preparation process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing anisotropic etching to create a recess portion with specific crystalline facet orientations before epitaxial growth. This pre-prepared trench bottom structure with controlled facets enables the subsequent epitaxy layers to grow flat surfaces, resolving the contradiction between surface flatness and process complexity.

Inventive Principle:
Principle #10Preliminary action

2Speed

If gate length is scaled down to increase drive current, then switching speed improves, but short-channel effects worsen and electrostatic control is compromised

Engineering Contradiction:
Improveswitching speedVSAvoidelectrostatic control
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent transitions from planar gate control to three-dimensional gate-all-around structure that wraps around the channel in multiple dimensions. This dimensional change provides superior electrostatic control over the shortened channel, enabling fast switching while maintaining reliability by controlling the channel from top, bottom, and sidewalls simultaneously.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If crystallographic anisotropic etching is used to create recess portions with specific facets, then epitaxy growth control improves, but the process complexity increases

Engineering Contradiction:
Improvecontrol over epitaxy growthVSAvoidease of trench fabrication
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by controlling the crystalline facet orientations and angles of the recess portion through anisotropic etching. By precisely adjusting these geometric parameters, the epitaxial growth is directed to form flat surfaces, achieving high manufacturing precision while managing process complexity through controlled parameter specification.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of GAA devices with flat surfaces and controlled epitaxy growth, enhancing electrostatic control and reducing short-channel effects, thereby improving the performance of CMOS transistors by allowing for more precise tuning of device parameters.

Implementation Method 1

modifying the trench bottom and sidewall facets through crystallographic anisotropic etching to create a recess with specific angles

Methodology Applied
Scientific EffectCrystallographic anisotropic etching: Anisotropy

Implementation Method 2

allowing for the growth of silicon germanium epitaxy layers that preferentially fill the trench bottom while avoiding the sidewalls

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11742405B2Separate epitaxy layers for nanowire stack GAA device
Publication Date: 2023.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11742405B2 patent drawing
  • US11742405B2 patent drawing
  • US11742405B2 patent drawing

AI summary

The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.