Nanowire Gate Structure with Aligned Edges for Reduced Parasitic Capacitance

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Solution Overview

Problem

The manufacturing of nanowires is challenging due to their three-dimensional nature and often results in high parasitic capacitance, making existing solutions non-manufacturable or inefficient.

Innovation Solution

A method involving patterning structures on a substrate, forming spacers, and etching to create controlled undercut portions, followed by the formation of source/drain regions and metal gate structures with aligned edges to minimize stray capacitance, is employed to fabricate nanowires with improved overlap capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If conventional nanowire fabrication methods are used, then three-dimensional nanowire structures can be formed, but high parasitic capacitance results

Engineering Contradiction:

Improvethree-dimensional nanowire structureVSAvoidparasitic capacitance

Core Design Contradiction:

ShapeVSObject-generated harmful factors

Solution Approach 1:

The gate structure is divided into top gate and bottom gate portions with aligned edges, segmenting the capacitance sources to reduce overlap capacitance while maintaining the three-dimensional nanowire configuration

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from conventional planar gate structures to a three-dimensional configuration with top and bottom gates positioned on opposite sides of the nanowire, utilizing vertical dimensionality to achieve edge alignment and reduce parasitic capacitance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If existing nanowire solutions are implemented, then device scaling is enabled, but manufacturing difficulty increases

Engineering Contradiction:

Improvedevice scaling capabilityVSAvoidfabrication difficulty

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Dummy structures are formed preliminarily during the fabrication process to define precise locations for subsequent etching and spacer formation, enabling controlled creation of the complex three-dimensional nanowire structure with aligned gates

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Spacer structures serve as intermediaries that precisely define the positions of top and bottom gates relative to the nanowire, enabling accurate edge alignment and reduced overlap capacitance through controlled deposition and etching processes

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10319860B2Overlap capacitance nanowire

Publication Date: 2019.06.11 ADEIA SEMICONDUCTOR SOLUTIONS LLC

AI summary

A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.