Stacked Nanowire Gate-Cut Isolation for Void-Free Metal Fill

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Solution Overview

Problem

The challenge in fabricating multi-gate transistors, such as tri-gate transistors, lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, with lithographic processes facing constraints due to the trade-off between feature pattern dimensions and spacing, particularly in bulk silicon substrates.

Innovation Solution

Implementing a 'plug-last' approach in the fin trim isolation process, where the metal gate is cut after gate dielectric and work function metal deposition, allowing for a seamless work function metal deposition without voids, by using anisotropic etching to remove the metal gate and fin/ribbon followed by dielectric fill, and forming isolation regions post-metal gate processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fin trim isolation process is used, then isolation regions are formed earlier in the process, but this creates voids and disrupts metal gate processing

Engineering Contradiction:

Improvemetal gate processing qualityVSAvoidfabrication process efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing the fin trim isolation process after metal gate deposition rather than before. This reverses the conventional sequence, allowing the metal gate to be deposited first without disruption from subsequent isolation formation, thereby eliminating voids and ensuring seamless coverage while maintaining fabrication efficiency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional process sequence by delaying the fin trim isolation step until after metal gate processing. This inversion resolves the contradiction by allowing isolation regions to be formed without interfering with metal gate deposition, eliminating void formation while maintaining overall process efficiency through the reversed timing

Inventive Principle:

Principle #13The other way round (Inversion)

2Manufacturing precision

If isolation regions are formed before metal gate deposition, then isolation is established early, but work function metal deposition has insufficient space and creates voids

Engineering Contradiction:

Improvework function metal deposition qualityVSAvoidprocess sequence complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by establishing the metal gate and work function metal layers before forming the isolation regions. This ensures that the metal deposition has adequate space and proper surface conditions, resulting in void-free, high-quality work function metal deposition while the subsequent isolation formation adds minimal complexity to the already-established metal structure

Inventive Principle:

Principle #10Preliminary action

3Reliability

If device dimensions are scaled down below 10nm, then short channel control is improved, but lithographic process constraints increase due to trade-off between feature size and spacing

Engineering Contradiction:

Improveshort channel controlVSAvoidlithographic process feasibility

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies dimensionality change by transitioning from planar transistor structures to vertically stacked three-dimensional transistor structures. This allows the channel length to be effectively extended in the vertical dimension while maintaining small lateral footprint, thereby achieving improved short channel control at scaled dimensions without imposing excessive constraints on lithographic process spacing requirements

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the negative impact on metal gate processing, ensures a void-free metal fill, and provides additional space for work function metal deposition, improving the fabrication process efficiency and quality of multi-gate transistors.

Implementation Method 1

performing an anisotropic etch to remove the gate stack under the opening

Methodology Applied

Scientific EffectAnisotropic etching:

Data Source

PatentUS20250113563A1Stacked nanowire transistor structures with isolation regions bound by gate cuts

Publication Date: 2025.04.03 INTEL CORP

AI summary

In one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. The second transistor device is spaced a first distance laterally from the first transistor device. The structure further includes a dielectric region between the first gate stack and the second gate stack. The dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.