Nanowire Gate Structure With Region-Specific Diameters
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Solution Overview
Problem
The reduction in transistor gate size leads to short channel effects and increased leakage current in semiconductor devices, which negatively impacts their electrical properties, and existing nanowire FETs face challenges in optimizing performance across core and peripheral devices due to self-heating and body effect issues.
Innovation Solution
A semiconductor structure and fabrication method involving first and second nanowires with different diameters formed over distinct regions of a substrate, with corresponding gate layers, to improve performance by managing self-heating and body effect in peripheral devices while maintaining low leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate size of transistor is reduced to increase device density, then device integration level is improved, but short channel effect increases and leakage current increases
Solution Approach 1:
The semiconductor substrate is divided into first region and second region with different nanowire configurations. The first region contains nanowires with first diameter optimized for core devices, while the second region contains nanowires with second diameter optimized for peripheral devices, allowing independent optimization of electrical properties for each device type
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different nanowire diameters tailored to their specific functional requirements. Core devices use nanowires with one diameter configuration to minimize leakage current, while peripheral devices use nanowires with another diameter configuration to reduce self-heating effects
2Reliability
If nanowire diameter is reduced to improve device performance, then short channel effect is reduced, but self-heating effect increases in peripheral devices
Solution Approach 1:
The patent implements different nanowire diameters in different regions: smaller diameter nanowires in the first region for core devices to minimize leakage, and larger diameter nanowires in the second region for peripheral devices to reduce self-heating. This local differentiation allows each region to be optimized for its specific operational characteristics
Solution Approach 2:
The semiconductor structure is segmented into distinct regions with different nanowire specifications. The first region uses nanowires with first diameter while the second region uses nanowires with second diameter, enabling independent thermal and electrical optimization for core and peripheral devices
3Ease of manufacture
If uniform nanowire diameter is used across all devices, then manufacturing complexity is reduced, but performance optimization for both core and peripheral devices cannot be achieved
Solution Approach 1:
The manufacturing process is segmented into region-specific steps: forming nanowires with first diameter in the first region and nanowires with second diameter in the second region. This segmentation enables performance optimization for different device types while maintaining a systematic fabrication approach
Solution Approach 2:
The patent applies local quality by configuring nanowires with different diameters in different regions based on their functional requirements. Core devices in the first region use nanowires optimized for low leakage current, while peripheral devices in the second region use nanowires optimized for reduced self-heating
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region; first nanowires formed over the first region of the semiconductor substrate; second nanowires with a diameter smaller than a diameter of the first nanowires formed over the second region of the semiconductor substrate; a first gate layer formed around the first nanowires; and a second gate layer formed around the second nanowires.