Nanowire Gate Structure With Reduced End Cap Capacitance
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the trade-off between the critical dimension of patterned features and spacing in multi-gate and nanowire transistors, leading to increased gate capacitance and complexity in lithographic processes, particularly as device dimensions scale below the 10 nanometer node.
Innovation Solution
The implementation of a metal gate process with a trench contact cut and plug structure, where a 'plug-last' approach allows for seamless work function metal deposition without voids, and the use of isotropic metal etch back to reduce gate end capacitance, enabling a self-aligned gate endcap architecture that minimizes endcap space and improves metal fill capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but gate capacitance increases and performance optimization becomes more difficult
Solution Approach 1:
The patent extracts and removes the gate end cap structure entirely by implementing trench contact cuts that extend through the gate electrode and gate dielectric layers. This elimination of the end cap reduces parasitic gate capacitance while maintaining device density benefits from scaling.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional trench contact structure that cuts through multiple layers vertically. This dimensional change allows the contact to reach through the gate stack without requiring lateral end cap extensions, thereby reducing capacitance while maintaining electrical connectivity.
2Quantity of substance
If feature size is reduced to increase functional unit density, then capacity increases, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent segments the gate structure into distinct regions with the trench contact cutting through the gate electrode and gate dielectric. This segmentation allows different portions of the gate to be independently processed and patterned, simplifying lithographic requirements while maintaining high functional unit density.
Solution Approach 2:
The trench contact cut is performed as a preliminary action before final gate electrode formation. By pre-defining the contact trenches through the gate dielectric and into the substrate, subsequent processing steps are simplified and lithographic constraints are reduced.
3Ease of manufacture
If conventional gate structure is used, then fabrication is simpler, but end cap space increases and metal fill capability decreases
Solution Approach 1:
The patent removes the traditional gate end cap structure by implementing trench contacts that cut through the gate stack. This extraction eliminates the need for end cap space while maintaining fabrication simplicity through standardized trench contact processing.
Solution Approach 2:
Instead of extending the gate electrode laterally to create end caps, the patent inverts the approach by cutting vertical trenches through the gate structure. This inversion eliminates lateral extensions while maintaining electrical connectivity, thereby reducing end cap space without complicating fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate end capacitance, enhances metal fill capability, and facilitates tighter endcap spacing, thereby improving device performance and reducing process variation, while maintaining seamless work function metal deposition.
Implementation Method 1
isotropic metal etch back to reduce gate end capacitance
Implementation Method 2
seamless work function metal deposition without voids
Data Source
AI summary
An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.