Nanowire Gate Structure With Isolation Layers for Low Parasitic Capacitance
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Solution Overview
Problem
The increasing demand for high integration of semiconductor devices poses challenges in achieving efficient transistor design and manufacturing, particularly in reducing parasitic capacitance and improving crystal quality while maintaining device reliability.
Innovation Solution
The semiconductor device design incorporates nanowires, gate electrodes, external spacers, and isolation layers, with specific arrangements and materials to reduce parasitic capacitance and enhance crystal quality, including the use of different dielectric materials and epitaxial growth techniques to form source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor structures are used to achieve high integration, then device density increases, but parasitic capacitance increases and crystal quality deteriorates
Solution Approach 1:
The transistor structure is segmented into distinct functional regions: source/drain regions formed by epitaxial growth, channel regions with nanowires, and isolation regions. This segmentation allows each region to be optimized independently - source/drain regions for carrier injection and collection, channel regions for transport, and isolation regions for electrical separation - thereby reducing parasitic capacitance while maintaining high integration density.
Solution Approach 2:
Different materials and structures are applied to different locations within the device. Epitaxial growth is used specifically in source/drain regions to achieve high crystal quality, while isolation layers are placed between adjacent transistors to reduce parasitic capacitance. The gate electrode structure is locally optimized to surround the nanowire channel, providing superior electrostatic control at the critical channel region.
2Reliability
If epitaxial growth is used to improve crystal quality in source/drain regions, then carrier mobility increases, but manufacturing complexity increases
Solution Approach 1:
Epitaxial growth is performed as a preliminary step before forming the gate electrode structure. The source/drain regions are pre-formed with high crystal quality through epitaxial growth, establishing the foundation for high carrier mobility before subsequent processing steps. This preliminary action allows the gate and other structures to be built upon already-optimized regions.
Solution Approach 2:
Isolation layers serve as intermediary structures between adjacent transistor units, providing electrical isolation and preventing parasitic capacitance formation. These intermediary elements enable the use of high-performance epitaxial source/drain regions without the negative effects of adjacent device interactions, thereby maintaining manufacturing feasibility while achieving high crystal quality.
3Reliability
If isolation layers are added between gate electrodes to reduce parasitic capacitance, then device reliability improves, but manufacturing steps increase
Solution Approach 1:
The isolation layer formation is merged with the gate electrode fabrication process. The same dielectric material is used for both the gate insulation and the isolation between adjacent gates, and these structures are formed in an integrated manner during the manufacturing process. This merging reduces the total number of discrete steps while achieving both gate functionality and parasitic capacitance reduction.
Solution Approach 2:
The dielectric material and formation process serve multiple functions: providing gate insulation, electrical isolation between adjacent transistors, and structural support for the gate electrode. This multi-functionality eliminates the need for separate isolation steps, reducing manufacturing complexity while maintaining the reliability benefits of reduced parasitic capacitance.
Data Source
AI summary
A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.