Nanowire Gate Structure Formed After Source/Drain
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce short channel effects and improve the performance of FinFET devices by forming a nanowire gate structure after source/drain formation, while maintaining manufacturing efficiency and reliability.
Innovation Solution
The method involves forming a fin with a sacrificial gate structure, creating sidewall spacers, removing the sacrificial gate to define a gate cavity, and performing a fin reflow process or hydrogen anneal to shape the fin into a nanowire structure, followed by forming a replacement gate structure around the nanowire.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is decreased to improve switching speed, then the operating speed of FETs is improved, but the short channel effect worsens
Solution Approach 1:
The patent transitions from planar FETs to FinFETs with vertically positioned fins, moving the channel structure into the third dimension. This vertical configuration allows for shorter channel lengths while maintaining effective gate control through the tri-gate structure that encloses the channel on three sides, thereby improving switching speed without severe short channel effects
Solution Approach 2:
The FinFET channel is segmented into multiple surfaces (front, back, and sides) that are independently controlled by the gate electrode. This segmentation of the channel control surfaces allows for better electrostatic control and reduced short channel effects even at reduced channel lengths
2Quantity of substance
If the physical size of FETs is reduced to increase device density, then the density of FETs on integrated circuit is increased, but the control over source and drain electrical potential worsens
Solution Approach 1:
By forming vertically positioned fins perpendicular to the substrate surface, the patent increases device density by stacking multiple channels vertically while maintaining effective gate control through the three-dimensional tri-gate structure that surrounds the channel on three sides
3Ease of manufacture
If a planar FET structure is used, then the manufacturing process is simpler, but the junction capacitance at drain region is higher causing short channel effects
Solution Approach 1:
The patent forms vertically positioned fins perpendicular to the substrate surface, creating a three-dimensional structure that reduces the junction capacitance at the drain region by separating the source and drain junctions in the vertical dimension, thereby reducing short channel effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces short channel effects and enhances device performance by creating a nanowire gate structure that improves switching speed and density, addressing the limitations of traditional planar FETs and enhancing manufacturing reliability.
Implementation Method 1
performing a fin reflow process on the exposed portions of the fin to define a nanowire structure
Implementation Method 2
performing a hydrogen anneal process on the exposed portions of the fin to define a nanowire structure
Data Source
AI summary
In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.