Nanowire Transistor Gate Spacer Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The downscaling of semiconductor devices has led to a short channel effect in transistors, reducing their reliability, and existing solutions, such as multi-gate structures, face challenges in optimizing performance due to parasitic capacitance and crystal quality issues in nanowire transistors.
Innovation Solution
A semiconductor device design featuring nanowire transistors with a specific configuration, including inner-insulating spacers between the gate dielectric layer and source/drain regions in one transistor type, and a different configuration without inner-insulating spacers in another, to reduce parasitic capacitance and enhance crystal quality, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner-insulating spacers are added between the gate dielectric layer and source/drain regions, then parasitic capacitance is reduced and reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate dielectric layer is segmented into two distinct parts: a first gate dielectric layer in contact with the source/drain region and a second gate dielectric layer surrounding the nanowire channel. This segmentation allows the first layer to provide electrical isolation (reducing parasitic capacitance) while the second layer maintains the gate's electrical function, thereby resolving the contradiction between reliability improvement and structural complexity.
2Productivity
If downscaling is performed to increase integration density, then productivity is improved, but short channel effect increases and reliability deteriorates
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures where the gate electrode completely surrounds the nanowire channel in multiple dimensions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects even at scaled dimensions, thus allowing continued productivity improvement through downscaling while maintaining reliability.
3Reliability
If multi-gate structures are used to reduce short channel effect, then reliability is improved, but parasitic capacitance increases and performance optimization becomes difficult
Solution Approach 1:
The first gate dielectric layer acts as an intermediary element between the source/drain region and the gate electrode. This intermediary layer provides electrical isolation that reduces parasitic capacitance formation, while still allowing the gate-all-around structure to maintain its effectiveness in controlling short channel effects, thus resolving the contradiction between reliability improvement and parasitic capacitance reduction.
Data Source
AI summary
A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.