Independent Nanowire Gate Stacks for Dense Low-Temperature DRAM
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Solution Overview
Problem
Current computational devices face challenges in achieving high device density and efficiency due to limitations in transistor scaling and material properties, particularly in maintaining performance at very low temperatures.
Innovation Solution
The development of independent gate stacks for single semiconductor structure transistors with vertically aligned semiconductor structures, allowing for reduced thickness and enhanced carrier mobility, along with active cooling systems to maintain low operating temperatures, enables efficient operation and increased density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor scaling is pursued to increase device density, then device density improves, but performance at very low temperatures deteriorates
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode) that can be independently controlled. This segmentation allows each gate to optimize carrier flow in different regions, maintaining performance at very low temperatures while enabling higher device density through vertical stacking.
Solution Approach 2:
The patent transitions from planar transistor scaling to vertical stacking with multiple gate electrodes stacked in the vertical dimension. This dimensional change allows increased device density without further reducing lateral feature sizes, thereby preserving low-temperature performance characteristics.
2Length of moving object
If semiconductor structure thickness is reduced to increase density, then device size decreases, but carrier mobility deteriorates
Solution Approach 1:
Different regions of the semiconductor structure are subjected to different doping concentrations (first doping concentration in first region, second doping concentration in second region). This local quality variation optimizes carrier mobility in specific regions while maintaining reduced overall thickness for high density.
Solution Approach 2:
The multiple independent gate electrodes can be dynamically controlled with different voltages to optimize carrier flow through the thin semiconductor structure, compensating for the reduced thickness and maintaining high carrier mobility despite the reduced dimension.
3Quantity of substance
If multiple gate electrodes are stacked vertically to increase density, then device density improves, but device complexity increases
Solution Approach 1:
Multiple gate electrodes are merged into a vertical stack sharing common source and drain regions. This combining approach increases device density while reducing the overall footprint and simplifying the layout compared to having separate planar transistors.
Solution Approach 2:
The vertically stacked gate structure serves multiple functions: each gate electrode can independently control carrier flow, the vertical stacking provides electrical isolation between gates, and the shared source/drain regions reduce overall device complexity. This multi-functionality resolves the contradiction between density and complexity.
Data Source
AI summary
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.