Parallel Nanowire Interconnect Cells for Fine-Grained Drive Tuning
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Solution Overview
Problem
The design of integrated circuits using standard cell libraries is labor-intensive and lacks the granularity needed for finer tuning of circuit parameters, particularly in finFET-based designs, which limits the flexibility and efficiency in adjusting drive power and other characteristics.
Innovation Solution
A method and toolset for designing circuits using nanowires or 2D material strips, allowing for finer granularity in transistor design by varying the number of nanowires or 2D material strips in parallel, enabling the creation of cell libraries with cells like inverters and NAND gates that can be optimized for specific performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If finFET-based standard cell libraries are used, then circuit design can be standardized and reused, but the granularity for tuning circuit parameters is insufficient and design flexibility is limited
Solution Approach 1:
The patent segments the channel structure into multiple independent fins, where each fin can be individually controlled. This allows the circuit designer to selectively enable or disable specific fins to achieve fine-grained tuning of transistor characteristics without redesigning the entire cell structure.
Solution Approach 2:
The patent introduces dynamic control mechanisms including switchable fins that can be turned on or off based on circuit requirements, and variable threshold voltage mechanisms that allow real-time adjustment of transistor characteristics. This dynamic adaptability enables the same cell structure to serve multiple design purposes.
2Power
If the number of fins is increased to adjust drive power, then transistor performance can be tuned, but the design process becomes more labor-intensive and time-consuming
Solution Approach 1:
The patent creates universal cell structures that can accommodate multiple drive power requirements through selective fin activation. A single cell design can be configured to provide different drive strengths by enabling different combinations of fins, eliminating the need to create multiple specialized cell variants.
Solution Approach 2:
The patent enables continuous parameter adjustment by allowing selective activation of individual fins with different characteristics. Designers can adjust effective channel width, threshold voltage, and drive current independently through different fin combinations, providing fine-grained control without creating new cell structures.
3Manufacturing precision
If complex reconfiguration of fins is performed to fine-tune circuit parameters, then circuit performance can be optimized, but the manufacturing and design complexity increases
Solution Approach 1:
The patent pre-configures multiple fins with different characteristics during manufacturing, including fins with different threshold voltages and drive strengths. The circuit designer can then simply select and activate the appropriate pre-configured fins for the desired performance, avoiding complex post-manufacturing reconfiguration.
Solution Approach 2:
The patent implements self-service mechanisms where the circuit automatically selects appropriate fin configurations based on operating conditions. Control logic monitors circuit performance and dynamically adjusts fin activation to maintain optimal operation without requiring external intervention or complex design processes.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.