3D Nanowire Memory Structure for Higher Current Retention
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Solution Overview
Problem
Current flash memory devices with three-dimensional structures face challenges in scaling due to reduced gate length, leading to decreased on-state current and increased electron velocity overshoot, which affects carrier scattering and data retention.
Innovation Solution
The semiconductor memory device employs a multi-level structure with nanowires stacked vertically, each memory transistor comprising at least two nanowires, and a gate-all-around architecture with oxide-nitride-oxide memory films to increase on-state current and improve data retention by enhancing carrier collision opportunities and reducing charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length is reduced to improve integration density, then device size is reduced, but on-state current decreases and electron velocity overshoot increases
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around (GAA) structures that completely surround the channel. This dimensional change allows the gate to control carriers from all directions (top, bottom, sides), significantly enhancing control efficiency and on-state current without increasing the planar footprint of the device.
Solution Approach 2:
The gate structure is nested around the channel in a concentric arrangement, with the gate completely surrounding the channel region. This nested configuration enables maximum gate control over the channel while maintaining compact device dimensions, directly addressing the contradiction between device size reduction and current maintenance.
2Area of moving object
If gate length is reduced to improve integration density, then device size is reduced, but electron velocity overshoot increases affecting carrier scattering
Solution Approach 1:
The gate-all-around structure extends control into the vertical dimension, surrounding the channel completely. This three-dimensional configuration increases the effective gate-channel interaction area and enhances carrier scattering through improved electrostatic control, counteracting the velocity overshoot effect that occurs with reduced gate lengths.
Solution Approach 2:
The patent employs composite material structures including oxide-nitride-oxide memory films and multi-layer gate dielectrics that optimize the electrical characteristics at the gate-channel interface. These composite structures enhance carrier scattering and control efficiency, compensating for the reduced gate length effects.
3Ease of manufacture
If conventional planar structure is used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent adopts vertical stacking of multiple nanowire channels and gate structures along the vertical axis, transitioning from two-dimensional planar layout to three-dimensional architecture. This enables significantly higher integration density by utilizing the vertical dimension for additional memory cells while maintaining compatibility with adapted CMOS manufacturing processes.
Solution Approach 2:
The memory structure is segmented into multiple discrete nanowire channels stacked vertically, with each nanowire forming an independent memory cell. This segmentation allows parallel processing and fabrication of multiple cells, improving integration density while enabling modular manufacturing approaches that build upon conventional processes.
Data Source
AI summary
A semiconductor memory device includes a plurality of nanowires vertically stacked over a substrate, and a plurality of memory films wrapping around the plurality of nanowires, respectively. Each of the memory films includes a first oxide layer, a nitride layer and a second oxide layer sequentially formed over the corresponding nanowire. The semiconductor memory device also includes a gate electrode layer surrounding the plurality of memory films, and an isolation structure encapsulating the gate electrode layer. The isolation structure is in direct contact with the gate electrode layer and the nitride layers of the memory films.