Gate-All-Around Nanowire Mobility via (110) Orientation
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Solution Overview
Problem
The challenge in fabricating gate-all-around integrated circuit structures is to achieve high mobility while maintaining short channel control as device dimensions scale below the 10 nanometer node, particularly with nanowires and nanoribbons, where stress transfer from metal gate electrodes is inefficient.
Innovation Solution
The use of a (110) wafer orientation in conjunction with a compressive metal gate electrode enhances the mobility of nanowire devices by imparting tensile channel stress along the transport direction and tensile vertical stress, effectively addressing the inefficiencies in stress transfer in traditional (100) wafer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional (100) wafer orientation with metal gate electrode is used, then device fabrication is simplified, but stress transfer to nanowire channel is inefficient and mobility improvement is limited
Solution Approach 1:
The patent changes the wafer orientation parameter from conventional (100) to (110) orientation. This parameter change fundamentally alters the crystallographic relationship between the metal gate electrode and the nanowire channel, enabling efficient stress transfer from the gate to the channel while maintaining fabrication simplicity. The (110) orientation provides specific atomic plane arrangements that facilitate mechanical coupling between the gate and channel structures.
Solution Approach 2:
The patent employs a composite structure consisting of metal gate electrode material combined with (110) oriented semiconductor substrate. This composite approach leverages the mechanical properties of the metal gate and the crystallographic properties of the (110) substrate to achieve both stress transfer efficiency and fabrication ease. The composite material system enables simultaneous optimization of stress coupling and manufacturability.
2Productivity
If device dimensions are scaled below 10 nanometer node, then device density increases, but maintaining short channel control and mobility improvement becomes challenging
Solution Approach 1:
The patent applies parameter changes by transitioning to (110) wafer orientation, which fundamentally alters the stress transfer mechanism at the nanoscale. This parameter change enables effective stress application to the channel even at sub-10nm dimensions, maintaining carrier mobility improvement despite extreme scaling. The crystallographic orientation provides inherent mechanical coupling that persists at smaller dimensions.
Solution Approach 2:
The patent addresses scaling challenges by introducing a dimensional aspect through crystallographic orientation. The (110) orientation provides a specific geometric configuration that enhances stress transfer in the vertical dimension while maintaining control over the horizontal channel dimensions. This dimensional approach through crystal orientation enables simultaneous achievement of high density and reliable short channel control.
3Reliability
If nanowire structures are used to improve short channel control, then device performance improves, but stress transfer from metal gate becomes inefficient
Solution Approach 1:
The patent resolves the stress transfer inefficiency in nanowire structures by changing the substrate orientation parameter to (110). This parameter change modifies the mechanical coupling between the metal gate and nanowire channel, enabling effective stress transfer despite the three-dimensional nanowire geometry. The (110) orientation provides optimal atomic plane alignment for stress transmission to the nanowire surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly boosts the performance of gate-all-around nanowire devices by improving channel mobility and device performance, as demonstrated by simulation data showing gains of up to 17% and 11% in Beta for nanowires and nanoribbons, respectively.
Implementation Method 1
The use of a (110) wafer orientation in conjunction with a compressive metal gate electrode enhances the mobility of nanowire devices by imparting tensile channel stress along the transport direction and tensile vertical stress
Data Source
AI summary
Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.