Semiconductor Nanowire Mobility Optimization via Oxidation
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Solution Overview
Problem
Current semiconductor nanowire manufacturing techniques struggle to achieve sublithographic dimensions and optimal mobility orientations, limiting the performance of semiconductor devices like CMOS circuits due to limitations in lithographic methods and varying oxidation rates across different crystallographic orientations.
Innovation Solution
The method involves patterning semiconductor structures with specific crystallographic orientations to maximize hole and electron mobility, followed by controlled oxidation to achieve sublithographic dimensions for semiconductor nanowires, compensating for different thinning rates across various crystallographic surfaces to ensure optimal widths without excessive or insufficient thinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic patterning is used to form semiconductor nanowires, then manufacturing capability is maintained, but sublithographic dimensions cannot be achieved
Solution Approach 1:
The manufacturing process is divided into two independent stages: first, lithographic patterning creates semiconductor structures with lithographic dimensions; second, oxidation selectively removes material to achieve the final sublithographic nanowire dimensions. This segmentation allows each stage to operate within its capability range while achieving the overall sublithographic target.
Solution Approach 2:
The lithographic patterning step creates preliminary semiconductor structures with dimensions larger than the final target. These structures serve as precursors that will be thinned by oxidation to reach the final sublithographic dimensions, allowing the lithography step to work within its capabilities while achieving beyond-lithographic final dimensions.
2Manufacturing precision
If oxidation is applied to thin semiconductor structures, then sublithographic dimensions are achieved, but different thinning rates occur across crystallographic orientations
Solution Approach 1:
The oxidation process is applied with awareness of local crystallographic variations. Different crystallographic orientations are recognized as having different oxidation rates, and the process parameters are adjusted or structures are designed to account for these local differences, ensuring uniform final dimensions despite varying local rates.
Solution Approach 2:
The oxidation process parameters (temperature, time, atmosphere composition) are optimized and controlled to minimize the impact of crystallographic orientation variations. By carefully controlling these parameters, the differential thinning rates are reduced, allowing achieving consistent sublithographic dimensions across different orientations.
3Manufacturing precision
If semiconductor structures are thinned to achieve sublithographic dimensions, then enhanced gate control is achieved, but mobility optimization becomes difficult
Solution Approach 1:
The semiconductor structures are designed with specific asymmetric crystallographic orientations that are known to enhance charge carrier mobility in desired directions. By carefully selecting and orienting crystal planes during the patterning and thinning processes, the structures achieve both the required sublithographic dimensions and optimized mobility characteristics for high-performance CMOS operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor nanowires with targeted sublithographic dimensions and optimized mobility orientations, enhancing the performance of semiconductor devices by improving charge transport and control, thereby achieving high on-current and low off-current in CMOS circuits.
Implementation Method 1
Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations
Data Source
AI summary
Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.