Nanowire MOS Gate Structure for Punch-Through Suppression
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while maintaining complexity and efficiency, particularly in the transition from planar to three-dimensional transistors, where existing methods struggle to effectively manage punch-through issues and optimize semiconductor layer stacks for improved performance.
Innovation Solution
The method involves fabricating N-type and P-type metal-oxide-semiconductor regions in IC devices using nanowires, with specific steps including substrate preparation, formation of semiconductor layer stacks, recessing isolation regions, and forming high-k/metal gate stacks around nanowires to enhance device performance and prevent punch-through, allowing for more efficient scaling and complexity in IC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in IC manufacturing, then manufacturing process is simpler, but device performance and scalability are limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional nanowire transistors by growing semiconductor nanowires vertically from the substrate. This dimensional change enables improved carrier transport, better gate control, and enhanced scalability while maintaining manufacturing feasibility through vapor-liquid-solid growth mechanisms.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into distinct nanowire channels with controlled diameters (e.g., 5-50 nm) that can be independently grown and processed. This segmentation allows for precise control of electrical properties while simplifying the overall fabrication process through self-organized growth patterns.
Solution Approach 2:
The patent utilizes parameter changes in the vapor-liquid-solid growth process, including temperature gradients, vapor pressure, and catalyst composition, to control nanowire diameter, length, and crystal orientation. These parameter adjustments enable scalable production of nanowires with tailored properties for different device applications.
3Productivity
If three-dimensional nanowire transistors are introduced, then device performance improves, but punch-through issues arise
Solution Approach 1:
The patent implements a nested structure where the gate electrode completely surrounds the nanowire channel in a wrap-around configuration. This nested geometry provides superior electrostatic control and prevents punch-through by maintaining strong electric field confinement throughout the channel length, even in short-channel devices.
Solution Approach 2:
The patent employs composite material structures including heteroepitaxial growth of different semiconductor materials (e.g., SiGe source/drain regions with Si channel) to create potential barriers that prevent carrier punch-through. The composite structure combines materials with different bandgaps and doping characteristics to enhance device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of more complex and efficient IC devices by preventing punch-through and optimizing semiconductor layer stacks, thereby improving the performance and scalability of ICs, addressing the limitations of existing methods in three-dimensional transistor fabrication.
Implementation Method 1
oxidizing first semiconductor layer stack to form first outer oxide layer and inner nanowire
Data Source
AI summary
An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.