Gate-All-Around Nanowire MOSFET Dummy Gate Removal
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Solution Overview
Problem
The formation of a gate-all-around nanowire structure in semiconductor devices is challenging due to difficulties in patterning the gate underneath the nanowire, leading to parasitic capacitance issues and inefficient electrostatic gate control.
Innovation Solution
A method involving the formation of a dummy gate stack over a nanowire, with recesses and spacers to limit undercutting, followed by removal of the dummy gate and deposition of a replacement gate that extends transverse to the nanowire, ensuring proper alignment and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy gate is formed as a sacrificial structure to facilitate patterning, then alignment and doping implantation are improved, but the undercutting during dummy gate removal extends the opening toward source and drain regions, adding parasitic capacitance
Solution Approach 1:
The patent forms recesses in the insulator layer before removing the dummy gate. These pre-formed recesses define the boundaries of the opening, preventing the undercutting from extending toward the source and drain regions. This preliminary structural preparation ensures that when the dummy gate is removed, the opening is confined within the recess boundaries, thus reducing parasitic capacitance while maintaining the alignment benefits of the dummy gate approach.
2Reliability
If the gate is patterned to surround the nanowire, then electrostatic gate control is improved, but it becomes difficult to pattern the portion of the gate underneath the nanowire
Solution Approach 1:
The patent introduces a dummy gate as an intermediary sacrificial structure that simplifies the patterning process. The dummy gate is formed using standard lithography and etching techniques, making it easy to manufacture. After the nanowire is released and positioned, the dummy gate is removed and replaced with the final gate structure. This intermediary approach allows the gate to ultimately surround the nanowire for improved electrostatic control, while the manufacturing complexity is managed through the temporary dummy structure.
Solution Approach 2:
The dummy gate is formed in advance as a placeholder structure that defines the gate position and dimensions before the nanowire is fully integrated. This preliminary gate structure enables subsequent steps such as nanowire release, spacer formation, and source/drain region definition to proceed with proper alignment. The dummy gate serves as a template that guides the formation of the final gate-all-around structure.
3Length of stationary object
If the bottom portion of the gate becomes longer than the top portion due to patterning difficulties, then the gate may overlap source and drain regions, but achieving proper gate length control becomes challenging
Solution Approach 1:
The patent forms recesses in the insulator layer before dummy gate removal. These recesses have predetermined dimensions that define the maximum extent of the opening. When the dummy gate is removed, the opening is confined within the recess boundaries, ensuring that the gate length is controlled and does not extend beyond the intended region toward the source and drain. This preliminary recess formation acts as a physical constraint that prevents gate length overrun.
Solution Approach 2:
The dummy gate serves as an intermediary structure that temporarily defines the gate region. Its length is precisely controlled during formation, and it serves as a reference for subsequent alignment steps. The spacer structures formed on either side of the dummy gate also act as intermediaries that define the boundaries of the opening, ensuring proper gate length control when the dummy gate is removed and replaced.
Data Source
AI summary
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.