Nanowire Gate Structure With Negative Capacitance for Parasitic Reduction
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Solution Overview
Problem
As semiconductor devices miniaturize, the increasing proximity of components leads to higher overlapping capacitances, particularly between the bottom substrate and gate, which is undesirable and needs to be reduced.
Innovation Solution
A nanowire/nanosheet device with a ferroelectric or negative capacitance material layer on the sidewall of the gate electrode is introduced, allowing for the adjustment of device characteristics such as threshold voltage and capacitance, achieved through the use of a ferroelectric or negative capacitance material in the form of a spacer or within a gate trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If device miniaturization is pursued to achieve further scaling, then device size is reduced and integration density is improved, but overlapping capacitances between components increase
Solution Approach 1:
A ferroelectric or negative capacitance material layer is introduced as an intermediary between the gate electrode and source/drain regions. This intermediate layer provides negative capacitance that compensates for the harmful overlapping capacitance, allowing miniaturization to proceed without proportionally increasing parasitic effects
Solution Approach 2:
The capacitance characteristic of the gate structure is changed by incorporating ferroelectric or negative capacitance material. This material exhibits negative capacitance behavior that actively reduces the total overlapping capacitance, transforming the electrical parameter of the gate-source/drain interface
2Quantity of substance
If spacing between components is reduced to increase integration density, then device capacity is improved, but capacitance between bottom substrate and gate increases
Solution Approach 1:
The ferroelectric or negative capacitance material layer serves as an intermediary that decouples the capacitive coupling between the gate and source/drain regions. This allows components to be placed closer together while the intermediate layer prevents excessive capacitance accumulation
Solution Approach 2:
The negative capacitance material is positioned in advance between the gate and source/drain to preemptively counteract the harmful capacitive coupling that would otherwise occur due to close spacing. This preliminary anti-action prevents the harmful effect before it can degrade device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the total capacitance by introducing negative capacitance between the gate and source/drain, potentially lowering the Subthreshold Swing to less than 60 mV/dec at 300K, thereby improving device performance and reducing overlapping capacitances.
Implementation Method 1
a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode
Implementation Method 2
The ferroelectric or negative capacitance material layer may be in a form of a spacer. Device characteristics, such as a threshold voltage (Vt), a Drain Induced Barrier Lowering (DIBL), a Subthreshold Swing (SS), etc., may be easily adjusted by adjusting a material of the ferroelectric or negative capacitance material layer.
Data Source
AI summary
A nanowire/nanosheet device having a ferroelectric or negative capacitance material and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the semiconductor device may include: a substrate; a nanowire/nanosheet on the substrate and spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and source/drain layers at opposite ends of the nanowire/nanosheet and adjoining the nanowire/nanosheet.