Nanowire and Planar FET Layout for Thick Gate Insulation
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Solution Overview
Problem
In semiconductor devices, it is challenging to simultaneously form nanowire-FETs and second FETs with a thick gate insulation film, as the small space between nanowire structures of nanowire-FETs makes it difficult to apply a thick gate insulation film to the second FET, and there is a need to apply reverse bias to control the threshold voltage of the second FET.
Innovation Solution
A semiconductor device design where the first field effect transistor has a nanowire or nanosheet structure with a gate insulation film and gate electrode, and the second field effect transistor has a channel forming layer with a gate insulation layer and gate electrode, with specific thickness and spacing relationships between the channel portions and gate insulation layers to accommodate both devices on the same base, allowing for a thick gate insulation film and reverse bias application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If nanowire structures are used to enable thin channel thickness for scaling, then device size is reduced and scaling is achieved, but the space between nanowire structures becomes so small that it is difficult to form a thick gate insulation film on the second FET
Solution Approach 1:
The patent divides the semiconductor device into two distinct regions: a first region containing nanowire-FETs with thin channels for low-voltage operation, and a second region containing planar-FETs with thick channels for high-voltage operation. This spatial segmentation allows each region to have optimized gate insulation film thickness independent of the other, resolving the contradiction between device scaling and gate insulation film formation.
Solution Approach 2:
The patent applies different structural configurations to different regions of the semiconductor device. The first region uses vertically stacked nanowire structures with thin channels suited for low-voltage operation, while the second region uses planar channel structures with thicker channels suitable for high-voltage operation. This local differentiation allows each region to have the appropriate gate insulation film thickness for its specific operational requirements.
2Ease of operation
If reverse bias is applied to control threshold voltage Vth of the second FET, then threshold voltage control is achieved, but the close spacing between nanowire structures makes it difficult to implement the necessary structure
Solution Approach 1:
The patent separates the device into functional regions where the second region is dedicated to planar-FETs that can accommodate reverse bias structures. This segmentation allows threshold voltage control mechanisms to be implemented in the second region without interfering with the nanowire structure in the first region, thus achieving ease of operation without excessive device complexity.
3Reliability
If a thick gate insulation film is formed on the second FET, then reliability is improved, but the small space between nanowire structures of the nanowire-FET prevents this
Solution Approach 1:
The patent creates separate operational regions where the second region is dedicated to planar-FETs that can accommodate thick gate insulation films for high-voltage operation. This segmentation allows the second region to achieve improved reliability through thicker gate insulation without constraining the overall device footprint, as the first region maintains the compact nanowire structure for low-voltage operation.
Data Source
AI summary
A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.