GAA FET SiGe Source/Drain Structure for Lateral Etch Control
Solution Overview
Problem
In semiconductor manufacturing, particularly for GAA FETs, controlling lateral etching during NW release is challenging due to insufficient etching budget, leading to issues with gate-to-drain capacitance and the need for defect-free source/drain epitaxial layers.
Innovation Solution
A novel method for fabricating source/drain epitaxial layers involves forming fin structures, etching sacrificial layers, and using epitaxial growth to create layers with varying Ge content and boron doping, with specific etching and annealing processes to ensure precise control and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for NW release, then the etching process is simple, but lateral etching control is insufficient leading to gate-to-drain capacitance issues
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etchants and parameters. First, a sacrificial layer is etched to create initial space, then a second etching step releases the nanowire while controlling lateral etching. This segmentation allows precise control over lateral etching at each stage rather than relying on a single aggressive etching step.
Solution Approach 2:
A sacrificial layer is deposited and patterned before the nanowire formation. This preliminary structure defines the exact region where lateral etching should occur, preventing unwanted lateral etching in other areas. The sacrificial layer acts as a mask that guides the subsequent etching process to achieve precise lateral control.
2Object-affected harmful factors
If insufficient etching budget is used, then gate-to-drain capacitance is reduced, but lateral etching control becomes challenging
Solution Approach 1:
The etching process uses multiple parameters including different etchants, temperatures, and exposure times for different etching steps. The first etching step uses one set of parameters optimized for removing the sacrificial layer, while the second step uses different parameters optimized for nanowire release with controlled lateral etching. This parameter optimization allows reducing gate-to-drain capacitance while maintaining lateral etching control.
3Reliability
If source/drain epitaxial layers are formed after NW release, then device performance is improved, but defect-free layer formation becomes difficult due to previous etching challenges
Solution Approach 1:
The carefully controlled and defect-free NW release process creates a clean surface preparation for the subsequent epitaxial growth. By preventing lateral etching defects and ensuring complete sacrificial layer removal, the method cushions against potential defects that would otherwise propagate into the epitaxial layers, ensuring high-quality defect-free source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances control over lateral etching, reduces gate-to-drain capacitance, and produces defect-free source/drain epitaxial layers, improving the performance and reliability of GAA FETs.
Implementation Method 1
a source/drain epitaxial layer is formed in the source/drain space
Implementation Method 2
with specific etching and annealing processes to ensure precise control and quality
Data Source
AI summary
A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.