Nanowire IC Routing Across Stacked Channel Layers
Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints in lithographic processes, and there is a need for improved interconnects across layers to enhance performance and bandwidth.
Innovation Solution
The use of horizontal atomic layer deposition (ALD) for forming metal layer interconnections across two layers of Si devices, specifically employing selective deposition techniques like W—SiN or Ru—SiCN, and implementing gate stack cuts, lateral connections, and dual epitaxial connections to facilitate improved routing and interconnects in nanowire-based devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate and nanowire transistors are scaled down to smaller dimensions, then device density is improved, but lithographic process constraints worsen
Solution Approach 1:
The patent transitions from planar 2D lithographic patterning to 3D vertical stacking architecture. By forming multiple layers of nanowire transistors stacked vertically, the device density increases without requiring proportionally smaller lithographic features. The vertical dimension provides an additional degree of freedom for increasing device capacity while maintaining lithographic process feasibility.
2Length of moving object
If critical dimension is reduced, then device scaling is improved, but spacing between features deteriorates
Solution Approach 1:
The invention utilizes vertical stacking to arrange multiple nanowire transistor layers in the z-direction, allowing features to be closely spaced in the lateral plane while maintaining adequate vertical separation. This enables reduced critical dimensions in the lithographic plane without compromising the spacing required between features, as the additional vertical dimension provides isolation and routing space.
3Productivity
If horizontal metal layer interconnections are implemented across layers, then routing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the interconnect structure into distinct horizontal metal layers that span across multiple nanowire transistor layers. Each metal layer is formed separately through selective deposition processes, allowing independent optimization of each interconnect level. This segmentation enables efficient routing across layers while managing complexity through modular, stepwise fabrication.
Solution Approach 2:
The patent introduces intermediate dielectric layers and selective mask structures as mediators between the nanowire transistor layers and metal interconnect layers. These intermediary elements facilitate the formation of horizontal connections across layers without directly complicating the nanowire device structures themselves, enabling routing efficiency while containing complexity in the interconnect formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient routing across layers, improving device performance, enhancing bandwidth, and reducing patterning complexity, thereby addressing the challenges of scaling and interconnect pitch in nanowire transistors.
Implementation Method 1
The use of horizontal atomic layer deposition (ALD) for forming metal layer interconnections across two layers of Si devices
Data Source
AI summary
Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.