Nanowire Structure Formation via Sacrificial Layer Etching
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Solution Overview
Problem
Maintaining device performance and good short channel control becomes challenging beyond the 14 nm technology node in semiconductor devices, necessitating new materials and integration schemes such as nanowires to enhance electron mobility and scaling.
Innovation Solution
A method involving the deposition and etching of alternating semiconductor and dielectric layers on a substrate to form a fin structure, which is then processed into a nanowire structure, utilizing epitaxial growth and selective etching techniques to create vertically stacked nanowires with improved electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional scaling is used beyond 14 nm node, then device feature size is reduced, but device performance and short channel control deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional nanowire structures. Multiple nanowires are stacked vertically to form a 3D active region, enabling continued scaling while maintaining electrical performance through the third dimension. This dimensional transition allows better electrostatic control and short channel effects management.
Solution Approach 2:
The semiconductor structure is divided into multiple discrete nanowire segments stacked vertically. Each nanowire acts as an independent conduction path, and the segmented structure enables better control of carrier flow and improved short channel characteristics compared to a single large planar channel.
2Speed
If new nanowire integration scheme is implemented, then electron mobility and device speed are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent forms alternating semiconductor and dielectric layers in advance before final nanowire release. This preliminary stacking and patterning of sacrificial layers simplifies the subsequent nanowire formation process by pre-establishing the vertical architecture and enabling self-aligned processing steps.
Solution Approach 2:
Sacrificial dielectric and semiconductor layers are used as intermediary structures during fabrication. These temporary layers guide the formation of the final nanowire structure and are selectively removed to release the nanowires, simplifying the overall integration process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective scaling of feature size, maintains good short channel control, and enhances device speed by forming a nanowire structure that integrates well into semiconductor devices, addressing performance challenges beyond the 14 nm node.
Implementation Method 1
depositing a first semiconductor layer on the substrate
Implementation Method 2
depositing a first semiconductor layer on the substrate
Implementation Method 3
etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure
Data Source
AI summary
Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer. The method further includes e) repeating a)-d) at least once, f) following e), repeating a)-c) once, g) etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure, and h) removing the patterned first semiconductor layers from the fin structure.