Nanowire Source-Drain Structure for Lower External Resistance
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Solution Overview
Problem
The challenge in nanowire semiconductor devices is to reduce external resistance (Rext) while maintaining mobility improvement and short channel control as device dimensions scale past the 15 nanometer node, which is crucial for increasing device capacity and performance.
Innovation Solution
The implementation of nanowire structures with non-discrete source and drain regions, where a pair of non-discrete source and drain regions is disposed on either side of the discrete channel regions, and methods such as increased doping, strain introduction, and epitaxial formation are used to improve contact area and reduce barriers, thereby decreasing external resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete source and drain regions are used in nanowire devices, then manufacturing is simpler, but external resistance is high
Solution Approach 1:
The patent merges discrete source and drain regions into continuous non-discrete source and drain regions that extend along the nanowire structure. This merging increases the contact area between the source/drain regions and the channel, thereby reducing external resistance while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
The patent transitions from one-dimensional discrete source and drain contacts to extended continuous regions that span multiple dimensions along the nanowire. This dimensional extension increases the effective contact area without significantly increasing device footprint, resolving the contradiction between resistance reduction and structural complexity.
2Productivity
If device dimensions are scaled down past 15nm node, then device density increases, but short channel control deteriorates
Solution Approach 1:
The patent implements a nested structure where the gate electrode stack completely surrounds the nanowire channel in a wrap-around configuration. This three-dimensional gate control provides superior short channel control compared to planar gates, enabling continued scaling below 15nm while maintaining effective channel control through the nested gate-channel geometry.
3Productivity
If device dimensions are scaled down past 15nm node, then device density increases, but mobility improvement is lost
Solution Approach 1:
The patent introduces strain into specific regions of the nanowire channel through the non-discrete source and drain structure. This localized strain engineering enhances carrier mobility in the channel region without affecting the overall device dimensions, allowing mobility improvement to be maintained even as device density increases through scaling.
Data Source
AI summary
Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.