Nanowire Cavity Spacer Layout for Leakage and Capacitance Control
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Solution Overview
Problem
Nanowire transistors with different channel widths in integrated circuits face challenges in achieving uniform alignment of cavity spacers with respect to the gate electrode, leading to performance issues such as current leakage and parasitic capacitance due to improper etching processes.
Innovation Solution
A two-part process for forming gate and cavity spacers, where a first spacer material is deposited over a dummy gate, and after removing the source and drain regions, a second spacer material is deposited to fill cavities between nanowires, which is then etched back to expose nanowire ends for epitaxial deposition of replacement source/drain materials, ensuring consistent alignment and compositionally different spacer materials are used for improved alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single spacer material and uniform etching process are used, then the process is simple, but uniform alignment of cavity spacers with the gate electrode cannot be achieved across nanowire transistors of different channel widths
Solution Approach 1:
The spacer formation process is divided into two distinct parts: a first spacer material deposited conformally over the dummy gate, and a second spacer material deposited after source/drain removal to fill cavities between nanowires. This segmentation allows each spacer to be independently optimized for its specific function, enabling uniform alignment across transistors of different channel widths while managing process complexity through systematic division of tasks.
Solution Approach 2:
Different spacer materials are used in different locations: the first spacer material is positioned along the gate electrode where precise alignment is critical, while the second spacer material fills the cavities between nanowires. This local differentiation of material properties and positions enables each region to contribute optimally to the overall alignment uniformity across varying channel widths.
2Reliability
If improper etching processes are used, then the process is fast, but current leakage and parasitic capacitance increase
Solution Approach 1:
The first spacer material is deposited conformally over the dummy gate before source and drain removal. This preliminary action creates a protective framework that guides subsequent etching processes, ensuring that the cavity spacers will align uniformly with the gate electrode while preventing harmful lateral etching that would cause leakage and parasitic capacitance.
Solution Approach 2:
The first spacer material acts as an intermediary structure between the dummy gate and the final cavity spacers. It mediates the etching process by providing a controlled reference surface that ensures precise alignment of the second spacer material with the gate electrode, thereby preventing leakage and parasitic capacitance while maintaining etching efficiency.
3Reliability
If cavity spacers are not uniformly aligned with the gate electrode, then manufacturing is easier, but parasitic capacitance and current leakage increase
Solution Approach 1:
The alignment process is segmented into two stages: first, conformal deposition of spacer material over the dummy gate establishes a precise reference framework; second, cavity spacer deposition occurs after source/drain removal with the first spacer already in place. This segmentation transforms a difficult single-step alignment into two manageable steps, reducing leakage and parasitic capacitance while maintaining ease of manufacture.
Solution Approach 2:
The first spacer material is deposited as a preliminary structure before the actual cavity spacers are formed. This preliminary action creates a stable reference framework that simplifies the subsequent alignment of cavity spacers with the gate electrode, making the overall process easier to manufacture while ensuring precise alignment to reduce leakage and parasitic capacitance.
Data Source
AI summary
A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.