GAA Nanowire Inner Spacer Layers for Gate-to-S/D Capacitance
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor structures around nanowire channels in semiconductor devices is challenging due to complexity in fabrication processes, particularly in reducing parasitic capacitance between the gate stack and source/drain features.
Innovation Solution
The formation of an inner spacer layer between the gate stack and source/drain features using a dielectric material with controlled etching, followed by selective treatment to create inner spacer layers with lower carbon concentration to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional fabrication processes are used for GAA transistors, then manufacturing simplicity is maintained, but parasitic capacitance between gate stack and source/drain features increases
Solution Approach 1:
The fabrication process is segmented into multiple distinct stages: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers (inner spacers), and selective removal. This segmentation allows precise control over the formation of low-k dielectric regions between the gate stack and source/drain features, effectively reducing parasitic capacitance while managing process complexity through systematic breakdown of steps.
Solution Approach 2:
Mandrels are formed in preliminary action as sacrificial structures that define the future positions of inner spacers. These mandrels are removed after spacer formation, leaving precisely positioned low-k dielectric regions. This preliminary action enables accurate placement of the inner spacers that will reduce parasitic capacitance without requiring complex direct patterning methods.
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing precision requirements increase
Solution Approach 1:
The spacer structures serve self-aligned functions where the first and second spacers automatically position themselves relative to the gate stack and source/drain features through conformal deposition processes. This self-alignment mechanism ensures precise dimensional control at scaled dimensions without requiring additional alignment steps, thereby maintaining manufacturing precision while supporting productivity through efficient single-step formations.
Solution Approach 2:
The patent employs parameter changes in the form of different dielectric materials with distinct k-values (first dielectric material with higher k, second dielectric material with lower k). By changing the dielectric parameter (k-value) rather than relying solely on dimensional scaling, the patent achieves parasitic capacitance reduction while maintaining feasible manufacturing precision requirements for the scaled device dimensions.
3Reliability
If inner spacer layers with lower carbon concentration are formed to reduce parasitic capacitance, then electrical performance improves, but fabrication process complexity increases
Solution Approach 1:
The mandrel structures are extracted or removed after serving their purpose as templates for inner spacer formation. This extraction leaves behind the second spacers (inner spacers) with controlled low-k dielectric properties positioned precisely between the gate stack and source/drain features. By taking out the sacrificial mandrels, the patent achieves the desired electrical performance improvement through parasitic capacitance reduction while managing fabrication complexity through the temporary use of removable template structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of GAA transistors by reducing parasitic capacitance, improving gate control, and mitigating short-channel effects, thereby supporting smaller and faster semiconductor devices.
Implementation Method 1
the treated portion of the dielectric material is etched to form inner spacer layers
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.