Nanowire Spacers for GAA Transistor Etch Selectivity
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Solution Overview
Problem
The existing methods for fabricating gate-all-around (GAA) transistors, particularly during the channel nanowire release process, face challenges such as degradation of device performance and increased processing complexity due to inadequate lateral etch control and etch selectivity issues, leading to voids in source/drain features and incomplete nanowire release.
Innovation Solution
The method involves forming nanowire spacers in the source and drain regions that function as etch stop layers during the channel nanowire release process, using a multi-layer nanowire spacer structure with different etching characteristics to enhance etch tuning windows and prevent lateral etching, thereby ensuring complete nanowire release and reducing fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-layer nanowire spacer structure is used, then fabrication process is simpler, but etch selectivity is insufficient leading to lateral etching and voids in source/drain features
Solution Approach 1:
The nanowire spacer structure is segmented into multiple layers (first nanowire spacer layer and second nanowire spacer layer) with different etching characteristics. This segmentation enables differential etching control during the channel nanowire release process, preventing lateral etching into source/drain regions while maintaining complete nanowire release. Each layer can be optimized for specific etch selectivity requirements.
Solution Approach 2:
Different regions of the nanowire spacer structure are assigned different materials with tailored etching properties. The first nanowire spacer layer uses a material with first etching characteristics optimized for protecting source/drain regions, while the second nanowire spacer layer uses a material with second etching characteristics optimized for enabling complete nanowire release. This local quality differentiation resolves the etch selectivity challenge.
2Reliability
If aggressive etching is used to ensure complete nanowire release, then nanowire release completeness improves, but lateral etching occurs causing voids in source/drain features
Solution Approach 1:
The multi-layer nanowire spacer structure acts as an intermediary mechanism that mediates between the conflicting requirements of complete nanowire release and source/drain feature protection. The first nanowire spacer layer serves as a protective intermediary that prevents lateral etching, while the second nanowire spacer layer enables complete nanowire release. This intermediary structure resolves the contradiction by providing controlled etch pathways.
Solution Approach 2:
The nanowire spacer structure employs composite materials with different etching characteristics arranged in multiple layers. This composite structure enables differential etching behavior where the first material layer protects source/drain regions from lateral etching while the second material layer allows complete nanowire release. The composite nature provides both protection and release functionality simultaneously.
Data Source
AI summary
Gate-all-around (GAA) devices and methods for fabricating such are disclosed herein. An exemplary GAA device includes a first semiconductor layer disposed over a substrate. A gate structure is disposed over and wraps a portion of the first semiconductor layer, such that the gate structure separates a source region of the first semiconductor layer and a drain region of the first semiconductor layer. A channel region of the first semiconductor layer is defined between the source region and the drain region. A dielectric layer is disposed adjacent to the first semiconductor layer, where the dielectric layer extends along an entirety of the source region of the first semiconductor layer and an entirety of the drain region of the first semiconductor layer. A second semiconductor layer disposed over the source region of the first semiconductor layer, the drain region of the first semiconductor layer, and the dielectric layer.