Nanowire Metallization Substrate Assembly for Secure Chip Mounting

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Solution Overview

Problem

Existing substrate arrangements for power semiconductor modules require complex and multi-step processes for securely mounting semiconductor elements, which can be inefficient and prone to mechanical and environmental damage.

Innovation Solution

A substrate arrangement featuring a first metallization layer with evenly distributed nanowires that form a permanent connection with semiconductor components, eliminating the need for additional adhesives or conductive layers by connecting the nanowires' ends to both the metallization layer and the components, allowing for flexible mounting and enhanced stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional mounting processes are used to securely mount semiconductor elements, then mechanical stability is achieved, but the manufacturing process becomes complex and multi-step

Engineering Contradiction:
Improvemechanical stabilityVSAvoidmounting process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions (mechanical support, electrical connection, and environmental protection) into a single integrated substrate structure. The substrate layer with its metallization layers provides both structural support and electrical pathways, eliminating the need for separate mounting procedures and additional adhesive layers, thus simplifying the manufacturing process while maintaining mechanical stability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate arrangement is designed to perform multiple functions simultaneously: the substrate layer provides mechanical support, the first metallization layer provides electrical connections to semiconductor elements, and the overall structure provides environmental protection. This multi-functionality reduces the number of discrete components and process steps required

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional adhesives or conductive layers are used to mount components, then secure mounting is achieved, but the number of process steps increases

Engineering Contradiction:
Improvemounting securityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The metallization layer is designed to simultaneously provide electrical conductivity and mechanical adhesion functions. By integrating these functions into a single layer formed through standard semiconductor manufacturing processes, the patent eliminates the need for separate adhesive application steps and additional conductive layer deposits, thereby improving manufacturing efficiency without compromising mounting security

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If complex multi-step processes are used for mounting, then secure connections are achieved, but the risk of mechanical and environmental damage increases

Engineering Contradiction:
Improveconnection securityVSAvoidmechanical and environmental damage risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The substrate structure is pre-configured with metallization layers and structural features during the substrate manufacturing process, before semiconductor elements are mounted. This preliminary preparation ensures that mounting requires minimal additional steps, reducing the exposure of components to potential mechanical damage from repeated handling and environmental factors from prolonged assembly time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240162129A1Substrate arrangement and methods for producing a substrate arrangement
Publication Date: 2024.05.16 INFINEON TECHNOLOGIES AG
  • US20240162129A1 patent drawing
  • US20240162129A1 patent drawing
  • US20240162129A1 patent drawing

AI summary

A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.