Nanowire Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
Maintaining device performance and short channel control becomes challenging beyond the 14 nm technology node in semiconductor manufacturing, particularly due to high parasitic capacitance and current leakage in nanowire transistors.
Innovation Solution
A method and structure for nanowire transistors involving the formation of a first dielectric layer with a lower dielectric constant and a second dielectric layer with a higher dielectric constant, strategically positioned between the substrate and nanowires to reduce parasitic capacitance and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nanowire transistors are used to achieve scaling and good short channel control, then device mobility and speed are enhanced, but parasitic capacitance and current leakage increase
Solution Approach 1:
The dielectric layer between the substrate and nanowire is segmented into two distinct layers: a first dielectric layer adjacent to the substrate and a second dielectric layer adjacent to the nanowire. This segmentation allows each layer to be optimized for different functions - the first layer for mechanical support and the second layer for electrical performance, thereby reducing parasitic capacitance while maintaining device speed
Solution Approach 2:
Different dielectric materials with different dielectric constants are used at different locations. The second dielectric layer (adjacent to the nanowire) uses a material with lower dielectric constant to minimize parasitic capacitance in the critical region, while the first dielectric layer (adjacent to substrate) can use materials with higher mechanical strength or different electrical properties, optimizing local properties for specific functional requirements
2Productivity
If nanowire transistors are scaled to maintain short channel control, then transistor density increases, but current leakage worsens
Solution Approach 1:
The two-layer dielectric structure acts as an intermediary between the substrate and the nanowire channel. This intermediate structure provides electrical isolation and controls the electric field distribution, preventing carrier leakage into the substrate while maintaining the scaled dimensions needed for high transistor density
Solution Approach 2:
The dielectric constant parameter is varied through the thickness of the dielectric structure, with the second layer (adjacent to nanowire) having a lower dielectric constant to reduce capacitive coupling and leakage currents, enabling scaled devices to maintain low leakage while achieving high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance and current leakage in nanowire transistors, enhancing device performance and mobility by optimizing the dielectric layers' placement and materials used.
Implementation Method 1
forming a second dielectric layer between first dielectric layer and the first nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer
Data Source
AI summary
Embodiments of the invention describe parasitic capacitance reduction structure for nanowire transistors and method of manufacturing. According to one embodiment the method includes providing a substrate, forming a first nanowire on the substrate, forming a second nanowire on the first nanowire, forming a first dielectric layer between the substrate and the first nanowire, and forming a second dielectric layer between first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer. According to one embodiment, a nanowire transistor includes a first nanowire on a substrate, a second nanowire on the second nanowire, a first dielectric layer between the substrate and the first nanowire, and a second dielectric layer between the first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer.