Nanowire Transistor Cell Library for FinFET Granularity
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Solution Overview
Problem
The design of integrated circuits using standard cell libraries is labor-intensive and lacks the granularity needed for finer tuning of circuit parameters, as existing technologies like finFETs have limited flexibility in adjusting transistor strength and circuit performance.
Innovation Solution
The use of nanowires or 2D material strips to form transistors and interconnects, allowing for the creation of cell libraries with cells that can vary in the number of nanowires or 2D material strips, enabling finer adjustments in drive power and performance characteristics, and the implementation of these cells in a computer-aided design tool for integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If finFETs are used with parallel fins to adjust transistor strength, then some design flexibility is achieved, but the granularity of circuit parameter tuning remains limited and complex reconfiguration is required for fine tuning
Solution Approach 1:
The transistor channel is segmented into multiple independent nanowire segments that can be individually controlled. Each nanowire segment acts as an independent transistor channel, allowing granular adjustment of transistor strength by selectively enabling or disabling individual segments through control gates, thereby achieving fine-tuning without complex reconfiguration
Solution Approach 2:
The nanowire transistor structure incorporates dynamically controllable segments where each nanowire can be independently switched on or off via control gates. This dynamic control enables real-time adjustment of transistor strength and circuit parameters without requiring physical reconfiguration, reducing design time while maintaining flexibility
2Power
If the number of parallel fins is increased or decreased to adjust drive power, then transistor strength can be modified, but the granularity of adjustment is insufficient for precise circuit parameter control
Solution Approach 1:
The channel is divided into multiple discrete nanowire segments, each controllable by its own control gate. This segmentation enables precise adjustment of drive power by selectively activating specific numbers and combinations of nanowire segments, providing fine-grained control over transistor strength and circuit parameters beyond what is possible with traditional parallel fin structures
Solution Approach 2:
The invention changes the fundamental parameter of channel structure from continuous fins to discrete nanowire segments. This parameter change enables continuous or near-continuous adjustment of drive power by varying the number of active nanowire segments, achieving precise circuit parameter control that was not possible with fixed-number parallel fin structures
3Reliability
If manual design and refinement of cells is performed by skilled designers, then cell performance can be optimized, but the process is labor-intensive and time-consuming
Solution Approach 1:
The nanowire transistor structure with its segmented, independently controllable channels provides self-adjusting capabilities through control gates. The structure inherently allows for programmable control of transistor characteristics, reducing the need for manual design iterations and skilled designer intervention while maintaining or improving cell performance optimization
Solution Approach 2:
By changing to nanowire-based transistors with independent control gates, the invention enables programmable control of circuit parameters directly through the device structure. This parameter control capability allows automated design tools to efficiently optimize cell performance without requiring extensive manual refinement, thereby improving design productivity while maintaining reliability
Data Source
AI summary
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.