Nanowire Transistor Custom Epitaxial Stacks for Strain Control
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Solution Overview
Problem
Existing nanowire transistor devices face challenges in maintaining mobility improvement and short channel control as device dimensions scale down, particularly due to strain relaxation issues that lead to defects and degraded performance in CMOS processes, where common layer stacks for p-type and n-type transistors are required to be identical in composition and thickness.
Innovation Solution
The technique involves replacing sacrificial fins with custom epitaxial material stacks of arbitrary composition and strain, allowing for independent p-type and n-type layer stacks, enabling diverse channel configurations and material systems within the same integrated circuit die, including custom thickness tuning and varying numbers of wires per transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common layer stacks with identical composition and thickness are used for p-type and n-type transistors, then manufacturing process simplicity is maintained, but device performance and reliability are degraded due to inability to independently optimize for each transistor type
Solution Approach 1:
The patent divides the previously unified layer stack into separate p-type and n-type layer stacks, allowing independent optimization of composition and thickness for each transistor type. This segmentation enables custom epitaxial material stacks with arbitrary composition and strain for each device type, resolving the contradiction between process simplicity and device performance.
Solution Approach 2:
The patent applies local quality by allowing different regions (p-type and n-type) to have different material compositions and layer structures. Each region can be independently tuned with custom thickness and composition to optimize performance for its specific transistor type, while still being part of the same integrated circuit die.
2Area of moving object
If device dimensions are scaled down, then integration density is improved, but short channel control and mobility improvement are lost due to strain relaxation issues
Solution Approach 1:
The patent changes material parameters by using custom epitaxial material stacks with arbitrary composition and strain. This allows maintaining strain-induced mobility improvement even as device dimensions scale down, preventing strain relaxation issues that would otherwise degrade short channel control at smaller dimensions.
3Reliability
If custom epitaxial material stacks with arbitrary composition and strain are used, then device performance and customization are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming custom epitaxial material stacks with the desired composition and strain characteristics before transistor fabrication. This pre-customization of material stacks allows subsequent standard fabrication processes to be used, managing complexity by resolving material optimization early in the process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant customization of nanowire stacks, providing a diverse range of configurations and material systems, thereby enhancing transistor performance by allowing independent optimization of p-type and n-type transistors, reducing defects, and improving yield and reliability.
Implementation Method 1
replacing sacrificial fins with custom epitaxial material stacks of arbitrary composition and strain
Data Source
AI summary
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.