Nanowire Transistor Gate Alignment via Self-Aligned Spacers
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Solution Overview
Problem
Existing methods for manufacturing transistors with semiconducting nanowires face challenges in achieving high density and precise gate alignment, leading to increased parasite capacitances and defects in source and drain regions due to non-self-aligned gate deposition and etching processes.
Innovation Solution
A method involving the use of self-aligned spacers formed from a dielectric layer, achieved through ion implantation and selective etching, which prevents gate material deposition in source and drain regions and maintains stress in the nanowire channel, ensuring precise gate alignment and reduced parasite capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a damascene type method (Gate-Last or Replacement Metal Gate) is used to form the gate by etching through a masking layer, then the gate can be formed around superposed nanowires, but the etching propagates towards the source and drain regions causing non-self-aligned gate deposition and increased parasite capacitances
Solution Approach 1:
The patent introduces spacers as intermediary elements positioned between the gate and source/drain regions. These spacers act as physical barriers that prevent gate material from depositing in the source and drain regions, thereby eliminating the harmful overlap and reducing parasite capacitances while maintaining proper gate alignment
Solution Approach 2:
The spacers are formed preliminarily before gate deposition. By pre-positioning the spacers to define the exact boundary where gate material should stop, the method ensures self-aligned gate formation without requiring complex etching control, thus improving manufacturing precision and preventing harmful overlaps
2Reliability
If restrictive design rules are applied to release silicon nanowires while maintaining the structure, then nanowire release is achieved, but the size of semiconductor blocks forming source and drain becomes large preventing high density of nanowires
Solution Approach 1:
The patent extracts the SiGe sacrificial layers selectively to release the silicon nanowires. By removing only the SiGe portions while preserving the silicon nanowire structure, the method achieves reliable nanowire release without requiring large semiconductor blocks, thus enabling high nanowire density in the final device structure
3Ease of manufacture
If etching is applied to eliminate SiGe at the channel region without self-alignment, then SiGe removal is achieved, but the final gate is not self-aligned with the volume formed by removal leading to increased parasite capacitances
Solution Approach 1:
The spacers serve as intermediary reference structures that remain after SiGe removal. These spacers provide precise positional references that guide subsequent gate formation processes, ensuring self-aligned gate deposition even though the SiGe removal itself is not self-aligned, thereby achieving both ease of manufacture and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of high-density transistors with improved electrical performance, reduced parasite capacitances, and minimized defects in source and drain regions, suitable for high-performance logic applications and GAAFET transistors with gate lengths less than 20 nm.
Implementation Method 1
first ion implantation in at least one second part of the first dielectric layer located between the first portion of the first nanowire and the support
Implementation Method 2
selective etching of the second part of the first dielectric layer, forming a second free space
Data Source
AI summary
Method of making a transistor with semiconducting nanowires, including:making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer,removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer,making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer,etching said second part, forming a second space,making a gate in the spaces, and a dielectric portion on the gate and said first parts,making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts,etch said fourth parts.