Compound Semiconductor Nanowire Transistors for Gate Length Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the integration density of semiconductor devices increases, the reliability and performance of transistors are affected due to decreasing gate lengths, requiring improved control over gate length and material phases in integrated circuit devices.
Innovation Solution
The integration of a compound semiconductor nanowire with alternating sections of different crystal phases, where a gate electrode and dielectric layer are formed between these sections, allowing for precise control of gate length and reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length of transistors is decreased to increase integration density, then the integration density is improved, but the reliability and performance of transistors deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertically-standing transistors with nanowire channels extending in the vertical direction. This dimensional change allows the gate to control the channel from the side rather than from above, enabling better electrostatic control at smaller gate lengths while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent employs compound semiconductor nanowires with alternating crystal phases (e.g., zinc blende and wurtzite phases) to create composite structures. These composite materials provide precisely controlled gate lengths through the alternating phases, improving transistor reliability by enabling better gate control while maintaining high integration density.
2Productivity
If the gate length of transistors is decreased to increase integration density, then the integration density is improved, but the performance of transistors deteriorates
Solution Approach 1:
By standing transistors vertically with nanowire channels extending upward, the gate wraps around the channel in a three-dimensional configuration. This provides superior electrostatic control that maintains high carrier mobility and fast switching speeds even as gate length decreases, thereby maintaining transistor performance while increasing integration density.
Solution Approach 2:
The alternating crystal phases in the nanowire create local variations in material properties along the channel. These local quality differences enable precise control of carrier transport properties, maintaining high-speed performance through optimized electron mobility in specific regions while keeping the overall gate length small for high density.
3Manufacturing precision
If compound semiconductor nanowires with alternating crystal phases are used, then gate length control precision is improved, but device complexity increases
Solution Approach 1:
The patent controls the crystal phase composition and alternating pattern in the nanowire by adjusting growth parameters such as temperature, pressure, and precursor ratios during chemical vapor deposition. By changing these parameters, precisely controlled gate lengths are achieved through the alternating phases, while the complexity is managed through process optimization rather than structural simplification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of integrated circuit devices by minimizing short-channel effects and power consumption, enabling faster carrier movement rates beyond the limits of silicon semiconductors.
Implementation Method 1
decreasing a width of the first section by selectively etching the first section from among the first section and the pair of second section in the compound semiconductor nanowire
Implementation Method 2
a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, with the first section and the second section having the same composition as each other and having different crystal phases from each other
Data Source
AI summary
An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.