Nanowire Transistor Gate Length Extension via Depletion Region
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Solution Overview
Problem
Existing semiconductor manufacturing processes are inadequate for scaling down transistor sizes effectively, as the depletion region induced by the gate structure does not extend sufficiently, limiting the effective channel length and transistor performance.
Innovation Solution
A semiconductor structure with a nanowire design that includes additional spaces between the source/drain regions and the gate structure, allowing the depletion region to extend beyond the physical gate length, thereby increasing the effective gate length and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the physical gate length is scaled down to increase integration density, then device size is reduced, but the depletion region cannot extend sufficiently to maintain effective channel length
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional nanowire structure where the gate completely surrounds the channel. This dimensional change allows the depletion region to extend vertically and radially beyond the physical gate boundaries, effectively increasing the channel length control without increasing the lateral device footprint.
Solution Approach 2:
The gate structure is nested around the nanowire channel in a concentric configuration. This nesting allows the gate to control the channel from multiple directions simultaneously, enabling the depletion region to extend further than the physical gate length would suggest in a planar configuration.
2Length of stationary object
If additional spaces are added between source/drain regions and gate structure, then effective gate length is increased, but device complexity increases
Solution Approach 1:
The patent creates a dynamic effective channel length that can be tuned by adjusting the spacing between source/drain regions and the gate structure. By controlling the depletion region extension into these spaces, the effective channel length becomes adjustable without changing the physical gate dimensions, allowing optimization for different operating conditions.
Solution Approach 2:
The patent modifies the geometric parameters of the nanowire structure, specifically the spacing between source/drain regions and the gate, to control depletion region behavior. By changing these dimensional parameters, the effective channel length is adjusted to achieve desired transistor performance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the effective gate length, leading to improved transistor performance, including a subthreshold slope close to 60 mV/decade and a higher current ratio between the 'on' and 'off' states, while maintaining a small physical gate length.
Implementation Method 1
a depletion region in the nanowire structure has a length longer than a length of the gate structure and does not contact the source region
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a nanowire structure formed over the substrate. In addition, the nanowire structure includes a first portion, a second portion, and a third portion. The semiconductor structure further includes a gate structure formed around the third portion of the nanowire structure and a source region formed in the first portion of the nanowire structure. In addition, a depletion region in the nanowire structure has a length longer than a length of the gate structure and is not in contact with the source region.