Variable Gate Width Nanowire Transistors via Inactive Channel Segmentation
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Solution Overview
Problem
Current semiconductor technologies face challenges in managing short-channel effects and varying gate width in nanowire-based transistors, which affect drive currents and leakage, especially as feature sizes shrink.
Innovation Solution
The development of nanowire-based gate all-around transistor structures with variable gate width is achieved by rendering certain nanowires inactive through channel portion severing or source/drain burial, allowing for the formation of a sacrificial gate structure that wraps around active nanowires, enabling control over gate width by adjusting the number of active and inactive nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width is increased to enhance drive currents, then the drive current increases, but the parasitic capacitance and short-channel effects worsen
Solution Approach 1:
The gate is segmented into multiple independent gates, each controlling a separate nanowire channel within the same fin structure. This allows the gate width to be effectively increased by activating more nanowires for higher drive current, while each individual gate maintains compact control to minimize parasitic capacitance and short-channel effects. The segmented gate structure enables selective activation of nanowires based on performance requirements.
2Productivity
If feature sizes are shrunk to achieve greater circuit density, then the circuit density increases, but the short-channel effects and off-state leakage increase
Solution Approach 1:
The invention transitions from planar 2D channel structures to three-dimensional nanowire channels arranged vertically within the fin. This dimensional change allows the channel to extend in the vertical dimension while maintaining a small lateral footprint, thereby increasing circuit density. The gate completely surrounds each nanowire channel, providing superior electrostatic control that suppresses short-channel effects and reduces off-state leakage even as feature sizes shrink.
3Adaptability or versatility
If the number of active nanowires is increased to vary gate width, then the gate width increases, but the device complexity increases
Solution Approach 1:
Multiple nanowire channels are pre-formed within the fin structure during the initial fabrication stages, with sacrificial materials positioned between them. The gate structure is then formed to wrap around all nanowires simultaneously. By controlling which nanowires are electrically connected and which remain isolated or disconnected, the gate width can be varied without requiring complex post-fabrication modifications. This preliminary arrangement of nanowires and sacrificial materials simplifies the overall fabrication process while enabling gate width variability.
Data Source
AI summary
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.