Nanowire Transistors With Graded Impurity Profiles
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Solution Overview
Problem
The short channel effect in multiple nanowire transistors leads to varying channel threshold voltages across nanowire patterns, resulting in deteriorated on-current characteristics due to differences in channel widths and impurity concentrations.
Innovation Solution
A semiconductor device design featuring nanowire patterns with varying channel widths and impurity concentrations, where channel regions at different distances from the substrate have equalized channel threshold voltages by adjusting impurity concentrations, and a gate electrode and dielectric film configuration to minimize short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple nanowire patterns are used to increase integration density, then device capacity increases, but channel threshold voltages vary across nanowire patterns causing on-current deterioration
Solution Approach 1:
The patent applies local quality by assigning different impurity concentrations to different nanowire patterns based on their specific positions and channel widths. Each nanowire pattern receives a tailored impurity concentration that compensates for its unique geometric characteristics, ensuring uniform threshold voltages across all patterns while maintaining high integration density
Solution Approach 2:
The patent changes the impurity concentration parameter across different nanowire patterns to compensate for variations in channel width and position. By adjusting this physical parameter locally, the invention equalizes channel threshold voltages and improves on-current characteristics without sacrificing device capacity
2Productivity
If nanowire patterns have different channel widths, then integration density improves, but channel threshold voltages become non-uniform
Solution Approach 1:
The patent implements local quality by customizing impurity concentrations for each nanowire pattern according to its specific channel width and position. This localized parameter adjustment ensures that narrower nanowires receive higher impurity concentrations to raise their threshold voltages, while wider nanowires receive lower concentrations to lower their threshold voltages, achieving uniformity across diverse geometries
3Reliability
If impurity concentrations are increased to raise channel threshold voltage, then threshold voltage increases, but carrier mobility decreases
Solution Approach 1:
The patent applies local quality by selectively increasing impurity concentrations only in specific nanowire patterns that require higher threshold voltages due to their narrow channel widths or positions, rather than uniformly increasing impurity concentrations across all nanowires. This targeted approach raises threshold voltages where needed while preserving carrier mobility in other regions
Data Source
AI summary
A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.