Nanowire Transistor Impurity Distribution for Threshold Voltage Control
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Solution Overview
Problem
Nanowire transistors face challenges in adjusting threshold voltage without degrading performance due to excessive impurity introduction, which leads to decreased on-state current and variability in threshold voltage, and constraints in manufacturing processes for optimal impurity concentration and gate electrode material selection.
Innovation Solution
A semiconductor device with a nanowire structure where the impurity concentration of the semiconductor substrate below the narrow portion is higher than the channel region, allowing for controlled threshold voltage adjustment through back gate bias while maintaining low impurity concentration in the channel region to reduce carrier scattering and variability, and optimizing the impurity concentration in source-drain regions to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If impurity is introduced to the channel region to adjust threshold voltage, then threshold voltage can be controlled, but on-state current decreases due to carrier scattering and threshold voltage variability increases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions with different impurity concentrations: a first region beneath the channel region with higher impurity concentration for threshold voltage control, and a second region beneath the source-drain regions with lower impurity concentration for maintaining high on-state current. This spatial segmentation allows independent optimization of each region's electrical characteristics without mutual interference.
Solution Approach 2:
The patent applies local quality by creating non-uniform impurity distribution across the semiconductor substrate. Specifically, the channel region's underlying substrate is doped with higher impurity concentration to enable threshold voltage adjustment, while the source-drain region's underlying substrate maintains lower impurity concentration to minimize carrier scattering and preserve high on-state current, thereby optimizing performance locally in each functional area.
2Measurement precision
If gate electrode material and impurity concentration are optimized for threshold voltage control, then threshold voltage adjustment improves, but manufacturing complexity increases due to process constraints
Solution Approach 1:
The patent performs preliminary impurity doping of the semiconductor substrate in different regions before forming the gate electrode. By pre-establishing the desired impurity concentration profiles in the channel and source-drain regions, the subsequent gate electrode formation and threshold voltage adjustment processes become simpler and more predictable, reducing manufacturing complexity while maintaining precise threshold voltage control.
Data Source
AI summary
A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.