Nanowire Transistor Fabrication via Sacrificial Layer Etching
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Solution Overview
Problem
Current semiconductor device manufacturing methods face challenges in achieving high density and controlling short channel effects in multi-gate transistors, particularly in forming precise three-dimensional channels and spacer structures.
Innovation Solution
A method involving the formation of stacked structures with sacrificial and semiconductor layers, followed by the creation of dummy gate and spacer structures, etching processes to form recesses, and the deposition of external and internal spacers to define nanowire channels and gate electrodes, allowing for precise control of channel dimensions and reduced fringing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with three-dimensional channel is formed to increase density, then device density and current control capability are improved, but manufacturing precision and structural complexity increase
Solution Approach 1:
The channel structure is segmented into multiple gates wrapping around a three-dimensional channel body (fin or nanowire), dividing the single-channel control into multiple gate-controlled segments. This segmentation enables better current control capability while maintaining high density through vertical stacking of source, channel, and drain regions.
Solution Approach 2:
The invention transitions from planar two-dimensional channel structures to three-dimensional channel structures with vertical stacking. The channel extends in the vertical dimension with multiple gates positioned at different heights, enabling increased device density while providing superior electrostatic control over the channel through the additional dimensional control points.
2Reliability
If multi-gate transistor with three-dimensional channel is formed to suppress short channel effect, then current control capability is improved, but device complexity increases
Solution Approach 1:
The multi-gate structure serves multiple functions simultaneously: it provides electrostatic control to suppress short channel effects, enables high current control capability through multiple control points, and achieves high device density through vertical stacking. The same three-dimensional channel structure fulfills multiple performance requirements that would otherwise require separate design elements.
Solution Approach 2:
The sacrificial layers are formed and positioned in advance before the actual channel and gate structures are created. These preliminary sacrificial structures guide the subsequent formation of the multi-gate transistor, enabling precise positioning of the three-dimensional channel and multiple gates while simplifying the overall fabrication sequence.
3Manufacturing precision
If precise three-dimensional channel and spacer structures are formed, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
Sacrificial layers serve as intermediary structures that facilitate the formation of precise three-dimensional channels and spacers. These temporary structures are formed first, then used as templates and masks for subsequent etching and deposition processes. After the actual channel and gate structures are formed, the sacrificial layers are removed, having served their purpose in achieving precise alignment without requiring complex direct patterning methods.
Solution Approach 2:
The sacrificial layers are replicated in multiple locations and configurations to create the stacked structure pattern. By forming identical sacrificial layer patterns that are then used as templates for etching, the invention achieves precise replication of the three-dimensional channel and spacer structures across the device, ensuring consistent alignment and dimensions through the copying process rather than requiring independent patterning of each structure.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.