Selective Amorphization for Nanowire Transistor Fabrication
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Solution Overview
Problem
Existing methods for producing transistors with semiconductor nanowires in a stack of superimposed layers face challenges such as restrictive design rules, significant source and drain block sizes, difficulty in achieving high nanowire density, and imprecise gate arrangement due to over-etching, leading to increased parasitic capacitances.
Innovation Solution
A method involving selective amorphization and etching of semiconductor materials in a stack structure, where ion implantations render specific areas amorphous, allowing for precise removal of certain semiconductor materials while preserving others, thereby avoiding over-etching and enabling accurate alignment and formation of a grid around the nanowires or bars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective removal of SiGe is carried out to free Si nanowires, then the nanowires are released for gate deposition, but the source and drain block sizes become significant and nanowire density is limited
Solution Approach 1:
The patent changes the physical state of SiGe from crystalline to amorphous through ion implantation, creating a selective amorphous layer that can be precisely removed. This parameter change enables better control over the removal process, allowing higher nanowire density while maintaining precise positioning, as the amorphous SiGe can be selectively etched without affecting the crystalline Si nanowires or requiring large source/drain blocks.
2Manufacturing precision
If damascene process is used to form gate after nanowire release, then the gate can be deposited in the cavity, but over-etching of SiGe occurs and reaches source and drain regions
Solution Approach 1:
The patent transforms SiGe into an amorphous state through ion implantation, creating a distinct physical state that can be selectively removed by etching. This parameter change allows precise control of the etching process to remove only the amorphous SiGe layer without damaging the crystalline Si nanowires or extending into the source and drain regions, thereby eliminating over-etching damage while achieving precise gate positioning.
3Manufacturing precision
If over-etching occurs during SiGe removal, then the gate arrangement becomes imprecise and non-uniform, but parasitic capacitances increase
Solution Approach 1:
By converting SiGe to an amorphous state through ion implantation, the patent creates a selectively removable layer with well-defined boundaries. This parameter change enables precise etching that removes only the intended SiGe regions without encroaching on source/drain areas, ensuring uniform and precise gate arrangement while minimizing parasitic capacitance caused by irregular gate positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of transistors with improved nanowire density and precise gate arrangement, reducing parasitic capacitances and enhancing the overall performance by avoiding over-etching and maintaining the crystalline structure of critical regions.
Implementation Method 1
making amorphous using one or more ion implantations, at least one area of the structure
Implementation Method 2
removing the portions based on the second semiconductor material rendered amorphous by selective etching of the second semiconductor material in amorphous form with respect to the first material semiconductor
Data Source
Figure 1~2C
Figure 2D~2E
Figure 2F~2I
AI summary
A method for manufacturing a transistor in which: a) at least one semiconductor structure is fabricated on a substrate, consisting of a stack comprising alternating layers (12, 12', 12") based on at least one first semiconductor material and layers (16, 16') based on at least one second semiconductor material different from the first semiconductor material; b) the amorphous region of the structure comprising one or more portions (161, 16'1) of one or more layers based on the second semiconductor material is rendered amorphous by means of implants; c) the portions (161, 16'1) are removed by selective etching of the second semiconductor material rendered amorphous with respect to the first semiconductor material.