Polycrystalline Nanowire Transistor Strain Engineering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of nanowire transistors on bulk substrates faces challenges due to crystal grain boundaries in the channel region, leading to inferior characteristics and large variations compared to those formed on SOI substrates, while using SOI substrates is costly.
Innovation Solution
A semiconductor device manufacturing method that involves forming an amorphous or polycrystalline semiconductor layer with a narrow portion, applying a strain-inducing insulating layer with a higher thermal expansion coefficient, and performing thermal treatment to crystallize the semiconductor layer under tensile strain, thereby improving transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a nanowire transistor is formed on a bulk substrate with a polycrystalline semiconductor layer, then manufacturing cost is reduced, but crystal grain boundaries appear in the channel region causing inferior characteristics and large variations
Solution Approach 1:
The patent applies strain to the polycrystalline semiconductor layer by forming a strained layer with different lattice constant or thermal expansion coefficient, thereby changing the physical state of the material to improve carrier mobility and suppress the harmful effects of crystal grain boundaries, resolving the contradiction between cost reduction and characteristic improvement
Solution Approach 2:
The patent uses a composite structure consisting of a polycrystalline semiconductor layer combined with a strained layer (such as silicon germanium or silicon nitride), creating a multi-material system that leverages the cost advantage of bulk substrates while achieving SOI-level performance through the strain-induced improvement in carrier transport properties
2Reliability
If a nanowire transistor is formed on an SOI substrate, then transistor characteristics are improved with strong resistance to short channel effect, but manufacturing cost increases
Solution Approach 1:
The patent replaces the expensive SOI substrate with a cheaper bulk substrate, using a polycrystalline semiconductor layer that can be formed on standard bulk silicon wafers, thereby achieving cost reduction while maintaining acceptable device performance through the introduction of strain
3Reliability
If the semiconductor layer is strained to improve on-current and reduce off-current, then transistor characteristics are enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The patent introduces strain into the semiconductor layer during the formation process itself, rather than requiring separate strain introduction steps after device fabrication. The strained layer is formed concurrently with or before the semiconductor layer, pre-establishing the strain condition that enhances carrier mobility and device characteristics
Solution Approach 2:
The patent uses a strained layer material (such as silicon germanium or silicon nitride) as an intermediary that transfers strain to the polycrystalline semiconductor layer. This intermediary layer serves as a strain source that indirectly improves the electrical characteristics of the channel region without requiring direct modification of the semiconductor material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances on-current, reduces off-current, and suppresses variations in transistor characteristics for both n-type and p-type transistors, while using a bulk substrate reduces manufacturing costs compared to SOI substrates.
Implementation Method 1
forming on the semiconductor layer an insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment
Implementation Method 2
performing thermal treatment; removing the insulating layer; forming a gate insulating film on the side faces of the narrow portion
Data Source
AI summary
A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.